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EDI88130CS/LPS-C PDF预览

EDI88130CS/LPS-C

更新时间: 2024-11-01 23:50:07
品牌 Logo 应用领域
其他 - ETC 电池静态存储器
页数 文件大小 规格书
9页 198K
描述
SRAM

EDI88130CS/LPS-C 数据手册

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EDI88130CS  
White Electronic Designs  
128Kx8 Monolithic SRAM, SMD 5962-89598  
FEATURES  
Access Times of 15*, 17, 20, 25, 35, 45, 55ns  
The EDI88130CS is a high speed, high performance,  
128Kx8 bits monolithic Static RAM>  
Battery Back-up Operation  
• 2V Data Retention (EDI88130LPS)  
An additional chip enable line provides system memory  
security during power down in non-battery backed up  
systems and memory banking in high speed battery  
backed systems where large multiple pages of mem-  
ory are required>  
CS1, CS2 & OE Functions for Bus Control  
Inputs and Outputs Directly TTL Compatible  
Organized as 128Kx8  
Commercial, Industrial and Military Temperature Ranges  
Thru-hole and Surface Mount Packages JEDEC Pinout  
• 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)  
• 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)  
• 32 lead Ceramic SOJ (Package 140)  
The EDI88130CS has eight bi-directional input-output  
lines to provide simultaneous access to all bits in a word>  
A low power version, EDI88130LPS, offers a 2V data  
retention function for battery back-up applications>  
Military product is available compliant to MIL-PRF-38535>  
*15ns access time is advanced information, contact factory for availabilityꢀ  
• 32 pad Ceramic Quad LCC (Package 12)  
• 32 pad Ceramic LCC (Package 141)  
• 32 lead Ceramic Flatpack (Package 142)  
Single +5V (±10%) Supply Operation  
FIGꢀ 1 PIN CONFIGURATION  
PIN DESCRIPTION  
32 DIP  
32 SOJ  
32 CLCC  
32 FLATPACK  
32 QUAD LCC  
TOP VIEW  
I/O0-7  
A0-16  
WE  
Data Inputs/Outputs  
Address Inputs  
Write Enable  
CS1, CS2  
OE  
Chip Selects  
TOP VIEW  
4
3
2
1
32  
31 30  
Output Enable  
Power (+5V ±10%)  
Ground  
5
6
29  
28  
27  
26  
25  
24  
23  
22  
21  
A
7
6
5
4
3
2
1
0
0
WE  
NC  
1
2
32  
31  
30 CS  
29 WE  
V
CC  
VCC  
A
A
A
A
A
13  
A16  
A14  
A12  
A
15  
7
VSS  
A
8
3
2
4
8
A
9
NC  
Not Connected  
A
7
6
5
4
3
2
1
5
28  
27  
26  
25  
A
A
A
A
13  
9
A
11  
A
6
8
10  
11  
12  
13  
A
OE  
A
A
A
A
A
7
9
8
11  
BLOCK DIAGRAM  
A
A
10  
9
24 OE  
23  
22 CS  
A
CS  
I/O  
1
10  
11  
12  
13  
14  
15  
A10  
I/O  
7
Memory Array  
1
A
Ø
Ø
21 I/O  
20 I/O  
19 I/O  
18 I/O  
17 I/O  
7
6
5
4
3
14  
15  
16  
17 18  
19  
20  
I/O  
I/O  
1
2
I/O  
V
SS 16  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
ÿ-16  
I/Oÿ-7  
WE  
CS  
CS  
1
2
OE  
1
White Electronic Designs Corporation • (602) 437-1520 • wwwꢀwhiteedcꢀcom  
March 2002 Revꢀ 11  

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