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EDI88128V20MM PDF预览

EDI88128V20MM

更新时间: 2024-02-02 17:19:30
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器光电二极管
页数 文件大小 规格书
5页 115K
描述
x8 SRAM

EDI88128V20MM 技术参数

生命周期:Obsolete包装说明:PLASTIC, SOJ-32
Reach Compliance Code:unknown风险等级:5.58
Is Samacsys:N最长访问时间:20 ns
JESD-30 代码:R-PDSO-J32内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:128KX8
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
认证状态:Not Qualified最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:J BEND
端子位置:DUALBase Number Matches:1

EDI88128V20MM 数据手册

 浏览型号EDI88128V20MM的Datasheet PDF文件第2页浏览型号EDI88128V20MM的Datasheet PDF文件第3页浏览型号EDI88128V20MM的Datasheet PDF文件第4页浏览型号EDI88128V20MM的Datasheet PDF文件第5页 
EDI88128V-RP  
HI-RELIABILITY PRODUCT  
128Kx8 Plastic Monolithic 3.3V SRAM  
FEATURES  
WEDC’s ruggedized plastic 128Kx8 SRAM allows the user to  
capitalize on the cost advantage of using a plastic component  
while not sacrificing all of the reliability available in a full military  
device.  
Access Times of 15, 20, 25ns  
TTL Compatible Inputs and Outputs  
Fully Static Operation  
Center Power and Ground Pins  
Industrial and Military Temperature Ranges  
Extended temperature testing is performed with the test patterns  
developed for use on WEDC’s fully compliant 128Kx8 SRAMs.  
WEDC fully characterizes devices to determine the proper test  
patterns for testing at temperature extremes. This is critical  
because the operating characteristics of device change when it is  
operated beyond the commercial temperature range. Using com-  
mercial test methods will not guarantee a device that operates  
reliably in the field at temperature extremes. Users of WEDC’s  
ruggedized plastic benefit from WEDC’s extensive experience in  
characterizing SRAMs for use in military systems.  
JEDEC Approved Revolutionary Pinout  
• 32 pin Plastic SOJ (Package 7)  
Single +3.3V (±10%) Supply Operation  
FIG. 1 PIN CONFIGURATION  
PIN DESCRIPTION  
TOP VIEW  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A0  
A1  
A2  
1
2
3
4
5
6
7
8
9
A16  
A15  
A14  
A13  
OE  
I/O7  
I/O6  
VSS  
I/O0-7  
A0-16  
WE  
CS  
Data Inputs/Outputs  
Address Inputs  
Write Enable  
A3  
CS  
I/O0  
I/O1  
Chip Select  
OE  
Output Enable  
Power (+3.3V ±10%)  
Ground  
VCC  
VSS  
VCC  
VCC  
VSS  
NC  
I/O2 10  
I/O3 11  
WE 12  
A4 13  
A5 14  
A6 15  
A7 16  
I/O5  
I/O4  
A12  
A11  
A10  
A9  
BLOCK DIAGRAM  
Not Connected  
Memory Array  
A8  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
Ø-16  
I/OØ-7  
WE  
CS  
OE  
1
July 1999 Rev. 1  
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  

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