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EDC4BV7242-70TG-S PDF预览

EDC4BV7242-70TG-S

更新时间: 2024-01-16 06:24:18
品牌 Logo 应用领域
富士通 - FUJITSU 光电二极管
页数 文件大小 规格书
8页 134K
描述
Memory IC, 4MX72, CMOS, PDMA168

EDC4BV7242-70TG-S 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM168针数:168
Reach Compliance Code:unknown风险等级:5.84
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-PDMA-N168内存密度:301989888 bit
内存宽度:72端子数量:168
字数:4194304 words字数代码:4000000
最高工作温度:70 °C最低工作温度:
组织:4MX72输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIMM
封装等效代码:DIMM168封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:3.3 V
认证状态:Not Qualified刷新周期:2048
座面最大高度:25.4 mm自我刷新:NO
最大待机电流:0.028 A子类别:Other Memory ICs
最大压摆率:1.72 mA标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

EDC4BV7242-70TG-S 数据手册

 浏览型号EDC4BV7242-70TG-S的Datasheet PDF文件第2页浏览型号EDC4BV7242-70TG-S的Datasheet PDF文件第3页浏览型号EDC4BV7242-70TG-S的Datasheet PDF文件第4页浏览型号EDC4BV7242-70TG-S的Datasheet PDF文件第6页浏览型号EDC4BV7242-70TG-S的Datasheet PDF文件第7页浏览型号EDC4BV7242-70TG-S的Datasheet PDF文件第8页 
November 1996  
Revision 1.0  
EDC4BV724(2/4)-(60/70)(J/T)G-S  
AC CHARACTERISTICS  
(TA = 0 to +70°C, VCC = 3.3V±0.3V, VSS = 0V)  
60  
70  
Parameter  
Symbol  
Unit  
Notes  
Min  
110  
-
Max  
Min  
130  
-
Max  
t
Random read/write cycle time  
Access time from RAS*  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
t
60  
70  
3,4  
3,4,5  
3, 10  
2
RAC  
t
Access time from CAS*  
-
20  
-
25  
CAC  
t
Access time from column address  
Transition time (rise and fall)  
RAS* precharge time  
-
35  
-
40  
AA  
t
2
50  
2
50  
T
t
40  
60  
20  
44  
10  
20  
14  
5
-
50  
70  
25  
49  
15  
20  
14  
5
-
RP  
t
RAS* pulse width  
10000  
10000  
RAS  
t
RAS* hold time  
-
-
RSH  
t
CAS* hold time  
-
-
CSH  
t
CAS* pulse width  
10000  
10000  
CAS  
t
RAS* to CAS* delay time  
RAS* to column address delay time  
CAS* to RAS* precharge time  
Row address set-up time  
Row address hold time  
45  
25  
-
50  
30  
-
4
RCD  
t
10  
RAD  
t
CRP  
t
5
-
5
-
ASR  
t
9
-
9
-
RAH  
t
Column address set-up time  
Column address hold time  
Column address to RAS* lead time  
Read command set-up time  
Read command hold time to CAS*  
Read command hold time to RAS*  
Write command hold time  
Write command pulse width  
Write command to RAS* lead time  
Write command to CAS* lead time  
Data-in set-up time  
0
-
0
-
ASC  
t
10  
35  
0
-
15  
40  
0
-
CAH  
t
-
-
RAL  
t
-
-
RCS  
t
0
-
0
-
8
RCH  
t
-1  
10  
10  
20  
10  
-1  
-
-1  
15  
15  
25  
15  
-1  
-
RRH  
t
-
-
WCH  
t
-
-
WP  
t
-
-
RWL  
t
-
-
CWL  
t
-
-
9
9
DS  
t
Data-in hold time  
15  
-
-
20  
-
-
DH  
2KR  
4KR  
32  
64  
-
32  
64  
-
t
Refresh period  
ms  
REF  
-
-
t
Write command set-up time  
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
7
1
1
WCS  
t
CAS* set-up time (CBR refresh)  
CAS* hold time (CBR refresh)  
RAS* precharge to CAS* hold time  
Access time from CAS* precharge  
Hyper page mode cycle time  
15  
9
-
15  
14  
4
-
CSR  
t
-
-
CHR  
t
4
-
-
RPC  
t
-
40  
-
45  
3, 11  
12  
CPA  
t
25  
10  
60  
-
30  
10  
70  
-
HPC  
t
CAS* precharge time (Hyper page)  
RAS* pulse width (Hyper page)  
-
-
CP  
t
100000  
100000  
RASP  
Fujitsu Microelectronics, Inc.  
5

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