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EC24C512CF2GT

更新时间: 2024-10-15 00:58:59
品牌 Logo 应用领域
飞虹 - E-CMOS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
16页 518K
描述
512K bits Two-wire Serial EEPROM

EC24C512CF2GT 数据手册

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EC24C512C  
512K bits Two-wire Serial EEPROM  
General Description  
EC24C512C. The bit stream over the SDA line includes a  
series of bytes, which identifies a  
The EC24C512C are EEPROM devices that use  
the industrial standard 2-wire interface for  
communications.  
particular Slave device, an instruction, an address within  
that Slave device, and a series of data, if appropriate. The  
EC24C512C also has a Write Protect pin (WP) to allow  
blocking any write operations over specified memory area.  
The EC24C512C also offers an additional page, named the  
Identification Page (128 bytes) which can be written and  
(later) permanently locked in Read-only mode. This  
Identification Page offers flexibility in the application board  
production line, as the Identification Page can be used to  
The EC24C512C contains a memory array of  
512K-bits (65,536x8), which is organized in 128-  
byte per page.  
The EEPROM can operate in a wide voltage  
range from 1.7V to 5.5V which fits most  
application. This product can provide a low- store unique identification parameters and/or parameters  
specific to the production line.  
Under no circumstance, the device will be hung up. In order  
to refrain the state machine entering into a wrong state  
power 2-wire EEPROM solution. The device  
is offered in Lead-free, RoHS, halogen free or  
Green. The available package types are 8-pin  
SOP, TSSOP, DFN.  
during power-up sequence or a power toggle off-on  
condition, a power on reset circuit is embedded. During  
power-up, the device does not respond to any instructions  
until the supply voltage (VCC) has reached an acceptable  
stable level above the reset threshold voltage. Once VCC  
passes the power on reset threshold, the device is reset  
and enters into the Standby mode. This would also avoid  
any inadvertent Write operations during power-up stage.  
During power-down process, the device will enter into  
standby mode, once VCC drops below the power on reset  
threshold voltage. In addition, the device will be in standby  
mode after receiving the Stop command, provided that no  
internal write operation is in progress. Nevertheless, it is  
illegal to send a command unless the VCC is within its  
operating level.  
The EC24C512C is compatible with the industrial  
standard 2-wire bus protocol. If in case the bus is  
not responded, a new sent Op-code command  
will reset the bus and the device will respond  
correctly. The simple bus consists of the Serial  
Clock wire (SCL) and the Serial Data wire  
(SDA). Utilizing such bus protocol, a Master  
device, such as a microcontroller, can usually  
control one or more Slave devices, alike this  
Features  
● Two-Wire Serial Interface, I2CTM Compatible  
Bi-directional data transfer protocol  
● Wide-voltage Operation  
● Page Size: 128 bytes  
● Page write mode  
Up to 128 bytes per page write  
- offer an 128 bytes additional page  
● Self timed write cycle with auto clear: 5ms (max.)  
● Filtered inputs for noise suppression  
● High-reliability  
VCC = 1.7V to 5.5V  
● Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V)  
uA, 1.7V  
● Operating current (max.): 0.5mA, 1.7V  
● Hardware Data Protection  
Endurance: 1 million cycles  
Data retention: 100 years  
Write Protect Pin  
● Industrial temperature grades  
● Packages: SOP,TSSOP,DFN  
● Lead-free, RoHS, Halogen free, Green  
● Sequential & Random Read Features  
● Memory organization: 65,536 x 8 bits  
E-CMOS Corp. (www.ecmos.com.tw)  
Page 1 of 16  
5C26N-Rev.F001  

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