Datasheet > EBJ81UG8EBU0

EBJ81UG8EBU0

更新时间： 2024-11-21 12:50:23

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
16页	229K
描述
8GB DDR3L SDRAM SO-DIMM

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数据手册

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EBJ81UG8EBU0 数据手册

DATA SHEET

8GB DDR3L SDRAM SO-DIMM

EBJ81UG8EBU0 (1024M words × 64 bits, 2 Ranks)

Specifications

Features

• Density: 8GB

• Organization

• Double-data-rate architecture: two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

1024M words × 64 bits, 2 ranks

prefetch pipelined architecture

• Mounting 16 pieces of 4G bits DDR3L SDRAM

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

sealed in FBGA

• Package: 204-pin socket type small outline dual

in-line memory module (SO-DIMM)

• DQS is edge-aligned with data for READs; center-

PCB height: 30.0mm

Lead pitch: 0.6mm

Lead-free (RoHS compliant) and Halogen-free

• Power supply: 1.35V (typ.)

VDD = 1.283V to 1.45V

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

Backward compatible for VDD = 1.5V ± 0.075V

• Data mask (DM) for write data

• Data rate: 1600Mbps/1333Mbps (max.)

Backward compatible to1066Mbps/800Mbps/667Mbps

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• Eight internal banks for concurrent operation

(components)

• On-Die-Termination (ODT) for better signal quality

Synchronous ODT

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

• /CAS write latency (CWL): 5, 6, 7, 8

Dynamic ODT

Asynchronous ODT

• Precharge: auto precharge option for each burst

• Multi Purpose Register (MPR) for pre-defined pattern

access

read out

• Refresh: auto-refresh, self-refresh

• Refresh cycles

• ZQ calibration for DQ drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• /RESET pin for Power-up sequence and reset

function

• SRT range:

Normal/extended

• Programmable Output driver impedance control

• Operating case temperature range

TC = 0°C to +95°C

Document No. E1812E30 (Ver. 3.0)

Date Published November 2011 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2011

12 3 4 5 6 7...16

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