Datasheet > EBJ81UG8BBU0-DJ-F

EBJ81UG8BBU0-DJ-F

更新时间： 2024-02-16 08:59:37

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
16页	152K
描述
8GB DDR3 SDRAM SO-DIMM

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技术参数
数据手册

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EBJ81UG8BBU0-DJ-F 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.75
Base Number Matches：	1

EBJ81UG8BBU0-DJ-F 数据手册

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DATA SHEET

8GB DDR3 SDRAM SO-DIMM

EBJ81UG8BBU0 (1024M words × 64 bits, 2 Ranks)

Specifications

Features

• Density: 8GB

• Double-data-rate architecture: two data transfers per

clock cycle

• Organization

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

1024M words × 64 bits, 2 ranks

• Mounting 16 pieces of 4G bits DDR3 SDRAM sealed

in FBGA

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• Package: 204-pin socket type small outline dual

in-line memory module (SO-DIMM)

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

PCB height: 30.0mm

Lead pitch: 0.6mm

• Differential clock inputs (CK and /CK)

Lead-free (RoHS compliant) and Halogen-free

• Power supply: VDD = 1.5V ± 0.075V

• DLL aligns DQ and DQS transitions with CK

transitions

• Data rate: 1600Mbps/1333Mbps (max.)

Backward compatible to1066Mbps/800Mbps/667Mbps

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Eight internal banks for concurrent operation

(components)

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• Interface: SSTL_15

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

• /CAS write latency (CWL): 5, 6, 7, 8

• On-Die-Termination (ODT) for better signal quality

Synchronous ODT

Dynamic ODT

• Precharge: auto precharge option for each burst

access

Asynchronous ODT

• Multi Purpose Register (MPR) for pre-defined pattern

read out

• Refresh: auto-refresh, self-refresh

• Refresh cycles

• ZQ calibration for DQ drive and ODT

Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset

function

• Operating case temperature range

TC = 0°C to +95°C

• SRT range:

Normal/extended

• Programmable Output driver impedance control

Document No. E1803E20 (Ver. 2.0)

Date Published September 2011 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2011

12 3 4 5 6 7...16

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