EBE10UE8AFSA-6E-F

更新时间： 2024-02-19 08:04:49

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
29页	251K
描述
1GB DDR2 SDRAM SO-DIMM

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数据手册

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EBE10UE8AFSA-6E-F 数据手册

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EBE10UE8AFSA

Byte No. Function described

Maximum data access time (tAC)

from clock at CL = X − 2

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

50H

0.5ns*¹

-8G (CL = 4)

-6E (CL = 3)

60H

3CH

0.6ns*¹

15ns

Minimum row precharge time (tRP)

Minimum row active to row active

delay (tRRD)

1EH

3CH

2DH

01H

7.5ns

Minimum /RAS to /CAS delay (tRCD) 0

15ns

Minimum active to precharge time

(tRAS)

45ns

Module rank density

1G bytes

Address and command setup time

before clock (tIS)

-8G

17H

20H

25H

27H

05H

0.17ns*¹

0.20ns*¹

0.25ns*¹

0.27ns*¹

0.05ns*¹

-6E

Address and command hold time

after clock (tIH)

-8G

-6E

Data input setup time before clock

(tDS)

-8G

-6E

10H

12H

0.10ns*¹

0.12ns*¹

Data input hold time after clock (tDH)

-8G

-6E

17H

3CH

0.17ns*¹

15ns*¹

Write recovery time (tWR)

Internal write to read command delay

(tWTR)

1EH

00H

7.5ns*¹

TBD

Internal read to precharge command

delay (tRTP)

Memory analysis probe

characteristics

Extension of Byte 41 and 42

Active command period (tRC)

06H

3CH

60ns*¹

Auto refresh to active/

Auto refresh command cycle (tRFC)

7FH

80H

14H

18H

1EH

127.5ns*¹

8ns*¹

SDRAM tCK cycle max. (tCK max.)

Dout to DQS skew

-8G

0.20ns*¹

0.24ns*¹

0.30ns*¹

-6E

Data hold skew (tQHS)

-8G

-6E

22H

00H

0.34ns*¹

PLL relock time

Undefined

Data Sheet E1450E20 (Ver. 2.0)

1...3 4 567 8 9...29

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