Datasheet > EBD11UD8ADDA-E

EBD11UD8ADDA-E

更新时间： 2022-11-25 15:23:22

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
19页	213K
描述
1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)

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数据手册

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EBD11UD8ADDA-E 数据手册

EBD11UD8ADDA-E

Timing Parameter Measured in Clock Cycle for unbuffered DIMM

Number of clock cycle

tCK

6ns

7.5ns

min.

Parameter

Symbol

tWPD

min.

max.

Unit

tCK

Write to pre-charge command delay (same

bank)

Read to pre-charge command delay

(same bank)

4 + BL/2

BL/2

3 + BL/2

BL/2

tRPD

tCK

Write to read command delay (to input all

data)

tWRD

2 + BL/2

Burst stop command to write command

delay

tBSTW

tCK

(CL = 2)

(CL = 2.5)

Burst stop command to DQ high-Z

(CL = 2)

tBSTW

tBSTZ

tCK

(CL = 2.5)

2.5

Read command to write command delay

(to output all data)

(CL = 2)

tRWD

2 + BL/2

tCK

(CL = 2.5)

Pre-charge command to high-Z

(CL = 2)

tRWD

tHZP

3 + BL/2

tCK

(CL = 2.5)

tHZP

2.5

tCK

Write command to data in latency

Write recovery time

tWCD

tWR

DM to data in latency

tDMD

tMRD

tSNR

tSRD

tPDEN

tPDEX

Mode register set command cycle time

Self refresh exit to non-read command

Self refresh exit to read command

Power down entry

200

Power down exit to command input

Data Sheet E0603E10 (Ver. 1.0)

1...11 12 131415 16 17...19

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