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LogiCORE PCI32 Interface v3.0
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DS 206 (v1.2) July 19, 2002
Data Sheet, v3.0.100
Introduction
LogiCORE Facts
1
With the Xilinx LogiCORE PCI Interface, a designer can
build a customized, fully PCI 2.3-compliant core with the
highest possible sustained performance, 528 Mbytes/sec.
PCI64 Resource Utilization
Slice Four Input LUTs
Slice Flip Flops
IOB Flip Flops
IOBs
724
732
176
89
Features
•
Fully PCI 2.3-compliant core, 64/32-bit, 66/33 MHz
interface
TBUFs
352
•
•
•
•
•
•
Customizable, programmable, single-chip solution
Predefined implementation for predictable timing
Incorporates Xilinx Smart-IP Technology
3.3 V operation at 0-66 MHz
2
GCLKs
1
1
PCI32 Resource Utilization
Slice Four Input LUTs
Slice Flip Flops
IOB Flip Flops
IOBs
553
566
97
5.0 V operation at 0-33 MHz
Fully verified design tested with Xilinx proprietary
testbench and hardware
50
TBUFs
288
•
Available for configuration and download on the web:
2
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Web-based Configuration and Download Tool
Web-based User Constraint File Generator Tool
GCLKs
1
Provided with Core
•
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CardBus compliant
Documentation
PCI Design Guide
Supported initiator functions:
PCI Implementation Guide
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Configuration Read, Configuration Write
Memory Read, Memory Write, MRM, MRL
Interrupt Acknowledge, Special Cycles
I/O Read, I/O Write
Design File Formats
Constraint Files
Verilog/VHDL Simulation Model
NGO Netlist
User Constraint Files (UCF)
Guide Files (NCD)
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Supported target functions:
Example Design
Verilog/VHDL Example Design
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Type 0 Configuration Space Header
Design Tool Requirements
Up to 3 Base Address Registers (MEM or I/O with
adjustable block size from 16 bytes to 2 Gbytes)
Xilinx Tools
v4.2i, Service Pack 3
Tested Entry and
Verification Tools
Synplicity Synplify
Synopsys FPGA Express
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-
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Medium Decode Speed
3
Parity Generation, Parity Error Detection
Configuration Read, Configuration Write
Memory Read, Memory Write, MRM, MRL
Interrupt Acknowledge
Exemplar Leonardo Spectrum
4
Xilinx XST
Cadence Verilog XL
Model Technology ModelSim
1. The resource utilization depends on configuration of the interface and the user
design. Unused resources are trimmed by the Xilinx technology mapper. The utili-
zation figures reported in this table are representative of a maximum configuration.
2. Designs running at 66 MHz in devices other than Virtex-II require one GCLKIOB
and two GCLKs.
I/O Read, I/O Write
Target Abort, Target Retry, Target Disconnect
3. See the implementation guide or product release notes for current supported ver-
sions.
4. XST is command line option only. See Implementation Guide for details.
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-
ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warran-
ties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS 206 (v1.2) July 19, 2002
www.xilinx.com
1
Data Sheet, v3.0.100
1-800-255-7778
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