Datasheet > DWC305

DWC305

更新时间： 2024-11-06 00:55:39

品牌	Logo	应用领域
FS		/
页数	文件大小	规格书
10页	297K
描述
Dual Bias ResistorTransistors

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数据手册

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DWC305 数据手册

SEMICONDUCTOR

DWC301~311

DWC317, 322, 323

TECHNICAL DATA

Dual Bias ResistorTransistors

NPN Silicon Surface Mount Transistors

with Monolithic Bias Resistor Network

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias

network consisting of two resistors; a series base resistor and a base–emitter resistor. These

digital transistors are designed to replace a single device and its external resistor bias network.

The BRT eliminates these individual components by integrating them into a single device. In

the DWC3xx series, two BRT devices are housed in the SOT–363 package which is ideal

for low power surface mount applications where board space is at a premium.

• Simplifies Circuit Design

• Reduces Board Space

SC-88/SOT-363

• Reduces Component Count

• We declare that the material of product compliance with RoHS requirements.

MAXIMUM RATINGS (T A = 25°C unless otherwise noted, common for Q 1 and Q 2 )

R₁

R₂

Q₂

Rating

Symbol Value

Unit

Vdc

Collector-Base Voltage

Collector-Emitter Voltage

Collector Current

V _CBO

V _CEO

I _C

R₂

Q₁

Vdc

R₁

100

mAdc

THERMAL CHARACTERISTICS

Characteristic

MARKING DIAGRAM

(One Junction Heated)

Total Device Dissipation

T _A= 25°C

Symbol

Max

Unit

P _D

187 (Note 1.)

256 (Note 2.)

1.5 (Note 1.)

2.0 (Note 2.)

670 (Note 1.)

490 (Note 2.)

mW/°C

°C/W

Derate above 25°C

Thermal Resistance –

Junction-to-Ambient

R _θJA

7X = Device Marking

(See Page 2)

Characteristic

(Both Junctions Heated)

Symbol

Max

Unit

DEVICE MARKING

INFORMATION

See specific marking information in

he device marking table on page 2 of

his data sheet.

Total Device Dissipation

T _A= 25°C

P _D

250 (Note 1.)

385 (Note 2.)

2.0 (Note 1.)

3.0 (Note 2.)

493 (Note 1.)

325 (Note 2.)

188 (Note 1.)

208 (Note 2.)

Derate above 25°C

mW/°C

°C/W

Thermal Resistance –

Junction-to-Ambient

Thermal Resistance –

Junction-to-Lead

R _θJA

R _θJL

°C/W

Junction and Storage

Temperature

T _J, T _stg

–55 to +150

°C

1. FR–4 @ Minimum Pad

2. FR–4 @ 1.0 x 1.0 inch Pad

2009. 12. 04

Revision No : 0

1/10

12 3 4 5 6 7...10

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