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DTC144TT1_05 PDF预览

DTC144TT1_05

更新时间: 2024-02-12 08:21:10
品牌 Logo 应用领域
安森美 - ONSEMI 晶体晶体管
页数 文件大小 规格书
4页 51K
描述
Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

DTC144TT1_05 数据手册

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DTC144TT1  
Preferred Devices  
Bias Resistor Transistor  
NPN Silicon Surface Mount Transistor  
with Monolithic Bias Resistor Network  
This new series of digital transistors is designed to replace a single  
device and its external resistor bias network. The BRT (Bias Resistor  
Transistor) contains a single transistor with a monolithic bias network  
consisting of two resistors; a series base resistor and a base−emitter  
resistor. The BRT eliminates these individual components by  
integrating them into a single device. The use of a BRT can reduce  
both system cost and board space. The device is housed in the SC−59  
package which is designed for low power surface mount applications.  
http://onsemi.com  
NPN SILICON BIAS  
RESISTOR TRANSISTOR  
PIN 3  
COLLECTOR  
(OUTPUT)  
Features  
PIN 2  
BASE  
(INPUT)  
R
R
1
Simplifies Circuit Design  
Reduces Board Space  
Reduces Component Count  
Moisture Sensitivity Level: 1  
ESD Rating: Human Body Model: Class 1  
ESD Rating Machine Model: Class B  
2
PIN 1  
EMITTER  
(GROUND)  
3
The SC−59 package can be soldered using wave or reflow. The  
modified gull−winged leads absorb thermal stress during soldering  
eliminating the possibility of damage to the die.  
Pb−Free Package is Available  
1
2
SC−59  
CASE 318D  
STYLE 1  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
A
Rating  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
Symbol  
Value  
50  
Unit  
Vdc  
V
V
CBO  
CEO  
MARKING DIAGRAM  
50  
Vdc  
I
100  
mAdc  
C
THERMAL CHARACTERISTICS  
Characteristic  
Symbol  
Max  
Unit  
8T M G  
Total Device Dissipation  
P
230 (Note 1)  
338 (Note 2)  
1.8 (Note 1)  
2.7 (Note 2)  
mW  
D
G
T = 25°C  
A
Derate above 25°C  
°C/W  
°C/W  
°C/W  
°C  
1
Thermal Resistance,  
Junction-to-Ambient  
R
q
JA  
540 (Note 1)  
370 (Note 2)  
8T = Specific Device Code  
M
G
= Date Code*  
= Pb−Free Package  
Thermal Resistance,  
Junction-to-Lead  
R
q
JL  
264 (Note 1)  
287 (Note 2)  
(Note: Microdot may be in either location)  
Junction and Storage Temperature  
Range  
T , T  
55 to +150  
J
stg  
*Date Code orientation may vary depending  
upon manufacturing location.  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
1. FR−4 @ Minimum Pad  
2. FR−4 @ 1.0 x 1.0 inch Pad  
Preferred devices are recommended choices for future use  
and best overall value.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
October, 2005 − Rev. 2  
DTC144TT1/D  
 

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