Datasheet > DSS5240V

DSS5240V

更新时间： 2024-11-14 09:57:47

品牌	Logo	应用领域
美台 - DIODES		晶体晶体管
页数	文件大小	规格书
5页	167K
描述
LOW VCE(SAT) PNP SURFACE MOUNT TRANSISTOR

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中文翻译

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DSS5240V 数据手册

DSS5240V

LOW V_CE(SAT)PNP SURFACE MOUNT TRANSISTOR

Features

Mechanical Data

•

Epitaxial Planar Die Construction

•

Case: SOT-563

Complementary NPN Type Available (DSS4240V)

Low Collector-Emitter Saturation Voltage, V_CE(SAT)

Surface Mount Package Suited for Automated Assembly

Ultra-Small Surface Mount Package

Lead Free/RoHS Compliant (Note 1)

"Green Device" (Note 2)

Case Material: Molded Plastic, “Green” Molding Compound. UL

Flammability Classification Rating 94V-0

Moisture Sensitivity: Level 1 per J-STD-020D

Terminals: Finish ⎯ Matte Tin annealed over Copper leadframe.

Solderable per MIL-STD-202, Method 208

Marking Information: See Page 4

Ordering Information: See Page 4

Weight: 0.003 grams (approximate)

•

1, 2, 5, 6

Bottom View

Device Schematic

Pin Out Configuration

Top View

Maximum Ratings @T_A= 25°C unless otherwise specified

Characteristic

Collector-Base Voltage

Symbol

V_CBO

V_CEO

V_EBO

I_C

Value

Unit

-40

-5

Collector-Emitter Voltage

Emitter-Base Voltage

Collector Current - Continuous

Peak Repetitive Collector Current (Note 3)

Peak Pulse Collector Current

Base Current (DC)

-1.8

-2

I_CRP

I_CM

-3

-300

-1

I_B

Peak Base Current

I_BM

Thermal Characteristics

Characteristic

Power Dissipation (Note 4) @ T_A= 25°C

Thermal Resistance, Junction to Ambient (Note 4) @ T_A= 25°C

Operating and Storage Temperature Range

Symbol

P_D

Value

600

Unit

°C/W

°C

208

R_θ

-55 to +150

T_J, T_STG

Notes:

1. No purposefully added lead.

2. Diode’s Inc.’s “Green” policy can be found on our website at http://www.diodes.com/products/lead_free/index.php.

3. Operated under pulse conditions: duty cycle ≤ 20%, pulse width tp ≤ 30ms.

4. Device mounted on FR-4 PCB with minimum recommended pad layout.

1 of 5

www.diodes.com

March 2009

DSS5240V

Document number: DS31673 Rev. 2 - 2

12 3 4 5

中文翻译

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