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DSPIC33EP64GS802T-I/PT PDF预览

DSPIC33EP64GS802T-I/PT

更新时间: 2024-11-13 02:37:31
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
484页 5042K
描述
16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators

DSPIC33EP64GS802T-I/PT 数据手册

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dsPIC33EPXXXGS70X/80X FAMILY  
16-Bit Digital Signal Controllers for Digital Power Applications with  
Interconnected High-Speed PWM, ADC, PGA and Comparators  
Operating Conditions  
Advanced Analog Features  
• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS  
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS  
• High-Speed ADC module:  
- 12-bit with four dedicated SAR ADC cores  
and one shared SAR ADC core  
Flash Architecture  
- Configurable resolution (up to 12-bit) for each  
ADC core  
• Dual Partition Flash Program Memory with  
LiveUpdate:  
- Up to 3.25 Msps conversion rate per channel  
at 12-bit resolution  
- Supports programming while operating  
- Supports partition soft swap  
- 11 to 22 single-ended inputs  
- Dedicated result buffer for each analog channel  
- Flexible and independent ADC trigger sources  
- Two digital comparators  
Core: 16-Bit dsPIC33E CPU  
• Code-Efficient (C and Assembly) Architecture  
• Two 40-Bit Wide Accumulators  
- Two oversampling filters for increased  
resolution  
• Single-Cycle (MAC/MPY) with Dual Data Fetch  
• Single-Cycle Mixed-Sign MUL plus  
Hardware Divide  
Four Rail-to-Rail Comparators with Hysteresis:  
- Dedicated 12-bit Digital-to-Analog Converter  
(DAC) for each analog comparator  
• 32-Bit Multiply Support  
• Four Additional Working Register Sets (reduces  
context switching)  
- Up to two DAC reference outputs  
- Up to two external reference inputs  
• Two Programmable Gain Amplifiers:  
- Single-ended or independent ground reference  
- Five selectable gains (4x, 8x, 16x, 32x and 64x)  
- 40 MHz gain bandwidth  
Clock Management  
• ±0.9% Internal Oscillator  
• Programmable PLLs and Oscillator Clock Sources  
• Fail-Safe Clock Monitor (FSCM)  
• Independent Watchdog Timer (WDT)  
• Fast Wake-up and Start-up  
Interconnected SMPS Peripherals  
• Reduces CPU Interaction to Improve Performance  
• Flexible PWM Trigger Options for  
ADC Conversions  
Power Management  
• Low-Power Management modes (Sleep,  
Idle, Doze)  
• High-Speed Comparator Truncates PWM  
(15 ns typical):  
• Integrated Power-on Reset and Brown-out Reset  
• 0.5 mA/MHz Dynamic Current (typical)  
• 20 μA IPD Current (typical)  
- Supports Cycle-by-Cycle Current-mode control  
- Current Reset mode (variable frequency)  
Timers/Output Compare/Input Capture  
High-Speed PWM  
• Five 16-Bit and up to Two 32-Bit Timers/Counters  
• Eight PWM Generators (two outputs per generator)  
• Individual Time Base and Duty Cycle for each PWM  
• Four Output Compare (OC) modules, Configurable  
as Timers/Counters  
• 1.04 ns PWM Resolution (frequency, duty cycle,  
dead time and phase)  
• Four Input Capture (IC) modules  
• Supports Center-Aligned, Redundant, Complementary  
and True Independent Output modes  
• Independent Fault and Current-Limit Inputs  
• Output Override Control  
• PWM Support for AC/DC, DC/DC, Inverters, PFC  
and Lighting  
2016-2018 Microchip Technology Inc.  
DS70005258C-page 1  

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