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DSPIC33CH128MP502 PDF预览

DSPIC33CH128MP502

更新时间: 2024-02-28 15:12:45
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
822页 7535K
描述
28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD)

DSPIC33CH128MP502 技术参数

生命周期:Active包装说明:SSOP, SSOP28,.3
Reach Compliance Code:compliantFactory Lead Time:8 weeks
风险等级:5.08其他特性:4k bytes internal data ram in slave core available
桶式移位器:YES位大小:16
边界扫描:YES最大时钟频率:64 MHz
格式:FLOATING POINT集成缓存:NO
内部总线架构:MULTIPLEJESD-30 代码:R-PDSO-G28
长度:10.2 mm低功率模式:YES
外部中断装置数量:4端子数量:28
片上数据RAM宽度:8片上程序ROM宽度:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCHRAM(字数):8192
ROM可编程性:FLASH筛选级别:TS 16949
座面最大高度:2 mm最大压摆率:300 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:5.3 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER

DSPIC33CH128MP502 数据手册

 浏览型号DSPIC33CH128MP502的Datasheet PDF文件第2页浏览型号DSPIC33CH128MP502的Datasheet PDF文件第3页浏览型号DSPIC33CH128MP502的Datasheet PDF文件第4页浏览型号DSPIC33CH128MP502的Datasheet PDF文件第5页浏览型号DSPIC33CH128MP502的Datasheet PDF文件第6页浏览型号DSPIC33CH128MP502的Datasheet PDF文件第7页 
dsPIC33CH128MP508 FAMILY  
28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers  
with High-Resolution PWM and CAN Flexible Data (CAN FD)  
Operating Conditions  
Power Management  
• 3V to 3.6V, -40°C to +125°C:  
- Master Core: DC to 90 MIPS  
- Slave Core: DC to 100 MIPS  
• 3V to 3.6V, -40°C to +150°C:  
- Master Core: DC to 60 MIPS  
- Slave Core: DC to 60 MIPS  
• Low-Power Management Modes  
(Sleep, Idle, Doze)  
• Integrated Power-on Reset and Brown-out Reset  
High-Resolution PWM with Fine Edge  
Placement  
• Up to 12 PWM Channels:  
- Four channels for Master  
- Eight channels for Slave  
• 250 ps PWM Resolution  
• Applications Include:  
Core: Dual 16-Bit dsPIC33CH CPU  
• Master/Slave Core Operation  
• Independent Peripherals for Master Core and  
Slave Core  
• Dual Partition for Slave PRAM LiveUpdate  
- DC/DC Converters  
• Configurable Shared Resources for Master Core  
and Slave Core  
- AC/DC power supplies  
- Uninterruptable Power Supply (UPS)  
- Motor Control: BLDC, PMSM, SR, ACIM  
• Master Core with 64-128 Kbytes of Program  
Flash with ECC and 16K RAM  
• Slave Core with 24 Kbytes of Program RAM  
(PRAM) with ECC and 4K Data Memory RAM  
Timers/Output Compare/Input Capture  
• Two General Purpose 16-Bit Timers:  
- One each for Master and Slave  
• Peripheral Trigger Generator (PTG) Module:  
- One module for Master  
• Fast Six-Cycle Divide  
• Message Boxes and FIFO to Communicate  
Between Master and Slave (MSI)  
• Code Efficient (C and Assembly) Architecture  
• 40-Bit Wide Accumulators  
- Slave can interrupt on select PTG sources  
- Useful for automating complex sequences  
• 12 SCCP Modules:  
• Single-Cycle (MAC/MPY) with Dual Data Fetch  
• Single-Cycle, Mixed-Sign MUL Plus Hardware  
Divide  
- Eight modules for Master  
• 32-Bit Multiply Support  
- Four modules for Slave  
• Five Sets of Interrupt Context Selected Registers  
and Accumulators per Core for Fast Interrupt  
Response  
- Timer, Capture/Compare and PWM Modes  
- 16 or 32-bit time base  
- 16 or 32-bit capture  
• Zero Overhead Looping  
- Four-deep capture buffer  
- Fully Asynchronous Operation, Available in  
Sleep Modes  
Clock Management  
• Internal Oscillator  
• Programmable PLLs and Oscillator Clock Sources  
• Master Reference Clock Output  
• Slave Reference Clock Output  
• Fail-Safe Clock Monitor (FSCM)  
• Fast Wake-up and Start-up  
• Backup Internal Oscillator  
• LPRC Oscillator  
2017-2019 Microchip Technology Inc.  
DS70005319D-page 1  

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