Datasheet > DSPIC33CH512MP505

DSPIC33CH512MP505

更新时间： 2024-02-05 00:51:42

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
814页	7352K
描述
48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data-Rate (CAN FD)

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dsPIC33CH512MP508 FAMILY

48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers

with High-Resolution PWM and CAN Flexible Data-Rate (CAN FD)

Operating Conditions

Power Management

• 3V to 3.6V, -40°C to +125°C:

- Master Core: DC to 90 MIPS

- Slave Core: DC to 100 MIPS

• 3V to 3.6V, -40°C to +150°C:

- Master Core: DC to 60 MIPS

- Slave Core: DC to 60 MIPS

• Low-Power Management Modes (Sleep, Idle,

Doze)

• Integrated Power-on Reset and Brown-out Reset

High-Resolution PWM with Fine Edge

Placement

• Up to Twelve PWM Channels:

- Four channels for Master

- Eight channels for Slave

• 250 ps PWM Resolution

Core: Dual 16-Bit dsPIC33CH CPU

• Master/Slave Core Operation

• Independent Peripherals for Master Core and

Slave Core

• Applications Include:

• Configurable Shared Resources for Master Core

and Slave Core

- DC/DC Converters

- AC/DC power supplies

• Master Core with 256-512 Kbytes of Program

Flash with ECC and 32-48K Data RAM with BIST

- Uninterruptable Power Supply (UPS)

- Motor Control: BLDC, PMSM, SR, ACIM

• Slave Core with 72 Kbytes of Program RAM (PRAM)

with ECC and 16K Data RAM with BIST

Timers/Output Compare/Input Capture

• Fast 6-Cycle Divide

• LiveUpdate

• Two General Purpose 16-Bit Timers:

- One each for Master and Slave

• Peripheral Trigger Generator (PTG) Module:

- One module for Master

• Message Boxes and FIFO to Communicate

Between Master and Slave (MSI)

• Code Efficient (C and Assembly) Architecture

• 40-Bit Wide Accumulators

- Slave can interrupt on select PTG sources

- Useful for automating complex sequences

• Twelve SCCP Modules:

• Single-Cycle (MAC/MPY) with Dual Data Fetch

• Single-Cycle, Mixed-Sign MUL Plus Hardware

Divide

- Eight modules for Master

• 32-Bit Multiply Support

- Four modules for Slave

• Five Sets of Interrupt Context Selected Registers

per Core for Fast Interrupt Response

- Timer, Capture/Compare and PWM modes

- 16 or 32-bit time base

• Zero Overhead Looping

- 16 or 32-bit capture

- 4-deep capture buffer

Clock Management

- Fully asynchronous operation, available in

Sleep modes

• Internal Oscillator

• Programmable PLLs and Oscillator Clock

Sources

• Master Reference Clock Output

• Slave Reference Clock Output

• Fail-Safe Clock Monitor (FSCM)

• Fast Wake-up and Start-up

• Backup Internal Oscillator

• LPRC Oscillator

 2018-2019 Microchip Technology Inc.

DS70005371D-page 1

12 3 4 5 6 7...814

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与DSPIC33CH512MP505相关器件

型号	品牌	获取价格	描述	数据表
DSPIC33CH512MP506	MICROCHIP	获取价格	48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN
DSPIC33CH512MP506-I/MR	MICROCHIP	获取价格	Microcontroller
DSPIC33CH512MP506-I/PT	MICROCHIP	获取价格	Microcontroller
DSPIC33CH512MP508	MICROCHIP	获取价格	48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN
DSPIC33CH512MP508-I/PT	MICROCHIP	获取价格	Microcontroller
DSPIC33CH64MP202	MICROCHIP	获取价格	28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM a
DSPIC33CH64MP202T-I/2N	MICROCHIP	获取价格	Digital Signal Processor, 16-Bit Size, 64MHz, CMOS, PQCC28
DSPIC33CH64MP203	MICROCHIP	获取价格	28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM a
DSPIC33CH64MP203T-I/M5	MICROCHIP	获取价格	Digital Signal Processor, 16-Bit Size, 64MHz, CMOS, PQCC36
DSPIC33CH64MP205	MICROCHIP	获取价格	28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM a

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