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DSPC56721AF PDF预览

DSPC56721AF

更新时间： 2024-11-09 15:42:07
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
54页 864K
描述
0-BIT, 200MHz, OTHER DSP, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-80

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DSPC56721AF 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：QFP包装说明：LQFP,
针数：80Reach Compliance Code：compliant
ECCN代码：3A001.A.3HTS代码：8542.31.00.01
风险等级：5.7其他特性：ALSO REQUIRES 3.3V I/O SUPPLY
地址总线宽度：桶式移位器：NO
边界扫描：YES最大时钟频率：200 MHz
外部数据总线宽度：格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PQFP-G80
JESD-609代码：e3长度：14 mm
低功率模式：NO湿度敏感等级：3
端子数量：80最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压：1.1 V最小供电电压：0.9 V
标称供电电压：1 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：14 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

DSPC56721AF 数据手册

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Freescale Semiconductor  
Data Sheet: Technical Data  
Document Number: DSP56720EC  
Rev. 5, 02/2009  
DSP56720/DSP56721  
DSP56720  
Symphony™  
DSP56720/DSP56721  
Multi-Core Audio Processors  
144-Pin LQFP  
20 mm × 20 mm  
0.5 mm pitch  
DSP56721  
80-Pin LQFP  
14 mm × 14 mm  
0.65 mm pitch  
144-Pin LQFP  
20 mm × 20 mm  
0.5 mm pitch  
The Symphony DSP56720/DSP56721 Multi-Core Audio  
Processors are part of the DSP5672x family of programmable  
CMOS DSPs, designed using multiple DSP56300 24-bit  
cores.  
Communication (ICC), an External Memory Controller  
(EMC) to support SDRAM, and a Sony/Philips Digital  
Interface (S/PDIF).  
The DSP56720/DSP56721 devices are intended for  
automotive, consumer, and professional audio applications  
that require high performance for audio processing. In  
addition, the DSP56720 is ideally suited for applications that  
need the capability to expand memory off-chip or to interface  
to external parallel peripherals. Potential applications include  
A/V receivers, HD-DVD and Blu-Ray players, car  
The DSP56720/DSP56721 offer 200 million instructions per  
second (MIPs) per core using an internal 200 MHz clock.  
The DSP56720/DSP56721 are high density CMOS devices  
with 3.3 V inputs and outputs.  
The DSP56720 device is slightly different than the DSP56721  
device—the DSP56720 includes an external memory  
interface while the DSP56721 device does not. The  
DSP56720 block diagram is shown in Figure 1; the  
DSP56721 block diagram is shown in Figure 2.  
audio/amplifiers, and professional recording equipment.  
The DSP56720/DSP56721 devices excel at audio processing  
for automotive and consumer audio applications requiring  
high MIPs. Higher MIPs and memory requirements are driven  
by the new high-definition audio standards (Dolby Digital+,  
Dolby TrueHD, DTS-HD, for example) and the desire to  
process multiple audio streams.  
In addition, DSP56720/DSP56721 devices are optimal for the  
professional audio market requiring audio recording, signal  
processing, and digital audio synthesis.  
The DSP56720/DSP56721 processors provide a wealth of  
on-chip audio processing functions, via a plug and play  
software architecture system that supports audio decoding  
algorithms, various equalization algorithms, compression,  
signal generator, tone control, fade/balance, level  
meter/spectrum analyzer, among others. The  
DSP56720/DSP56721 devices also support various matrix  
decoders and sound field processing algorithms.  
With two DSP56300 cores, a single DSP56720 or DSP56721  
device can replace dual-DSP designs, saving costs while  
meeting high MIPs requirements. Legacy peripherals from the  
previous DSP5636x/7x families are included, as well as a  
variety of new modules. Included among the new modules are  
an Asynchronous Sample Rate Converter (ASRC), Inter-Core  
Freescale reserves the right to change the detail specifications as may be required to permit  
improvements in the design of its products.  
© Freescale Semiconductor, Inc., 2009. All rights reserved.  
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