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DS90UB926QSQX

更新时间: 2024-11-15 12:55:27
品牌 Logo 应用领域
德州仪器 - TI 光电二极管
页数 文件大小 规格书
57页 1171K
描述
5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel

DS90UB926QSQX 数据手册

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DS90UB926Q  
5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional  
Control Channel  
General Description  
Features  
The DS90UB926Q deserializer, in conjunction with the  
DS90UB925Q serializer, provides a complete digital interface  
for concurrent transmission of high-speed video, audio, and  
control data for automotive display and image sensing appli-  
cations.  
Bidirectional control interface channel interface with I2C  
compatible serial control bus  
Supports high definition (720p) digital video format  
RGB888 + VS, HS, DE and synchronized I2S audio  
supported  
This chipset translates a parallel RGB Video Interface into a  
single pair high-speed serialized interface. The serial bus  
scheme, FPD-Link III, supports full duplex of high speed for-  
ward data transmission and low speed backchannel commu-  
nication over a single differential link. Consolidation of video  
data and control over a single differential pair reduces the in-  
terconnect size and weight, while also eliminating skew issues  
and simplifying system design.  
5 to 85 MHz PCLK supported  
Single 3.3V Operation with 1.8V or 3.3V compatible  
LVCMOS I/O interface  
AC-coupled STP Interconnect up to 10 meters  
Parallel LVCMOS video outputs  
I2C compatible serial control bus for configuration  
DC-balanced & scrambled Data w/ Embedded Clock  
The DS90UB926Q deserializer recovers the RGB data, three  
video control signals and four synchronized I2S audio signals.  
It extracts the clock from a high speed serial stream. An output  
LOCK pin provides the link status if the incoming data stream  
is locked, without the use of a training sequence or special  
SYNC patterns, as well as a reference clock.  
Adaptive cable equalization  
Supports repeater application  
@ SPEED Link BIST Mode and LOCK status pin  
Image Enhancement (White Balance and Dithering) and  
Internal pattern generation  
EMI Minimization (SSCG and EPTO)  
The DS90UB926Q deserializer has a 31-bit parallel LVCMOS  
output interface to accommodate the RGB, video control, and  
audio data.  
Low power modes minimize power dissipation  
Automotive grade product: AEC-Q100 Grade 2 qualified  
An adaptive equalizer optimizes the maximum cable reach.  
EMI is minimized by output SSC generation (SSCG) and en-  
hanced progressive turn-on (EPTO) features.  
>8kV HBM and ISO 10605 ESD rating  
Backward compatible to FPD-Link II  
Applications  
Automotive Display for Navigation  
Rear Seat Entertainment Systems  
Automotive Drive Assistance  
Automotive Megapixel Camera Systems  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
PRODUCTION DATA information is current as of  
publication date. Products conform to specifications per  
the terms of the Texas Instruments standard warranty.  
Production processing does not necessarily include  
testing of all parameters.  
301434 SNLS422  
Copyright © 1999-2012, Texas Instruments Incorporated  

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