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DS90C124IVSX/NOPB PDF预览

DS90C124IVSX/NOPB

更新时间： 2024-09-26 11:10:31
品牌 Logo 应用领域
德州仪器 - TI 光电二极管接口集成电路
页数 文件大小 规格书
41页 1802K
描述
5MHz 至 35MHz 直流平衡 24 位 FPD-Link II 解串器 | PFB | 48 | -40 to 105

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DS90C124IVSX/NOPB 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active包装说明：TQFP-48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.28Is Samacsys：N
差分输出：NO输入特性：DIFFERENTIAL
接口集成电路类型：LINE RECEIVER接口标准：GENERAL PURPOSE
JESD-30 代码：S-PQFP-G48JESD-609代码：e3
长度：7 mm湿度敏感等级：3
功能数量：1端子数量：48
最高工作温度：105 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP48,.35SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：
接收器位数：1筛选级别：AEC-Q100
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大压摆率：75 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
电源电压1-最大：3.6 V电源电压1-分钟：3 V
电源电压1-Nom：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

DS90C124IVSX/NOPB 数据手册

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Support &  
Community  
Product  
Folder  
Order  
Now  
Tools &  
Software  
Technical  
Documents  
DS90C124, DS90C241  
SNLS209M –NOVEMBER 2005–REVISED JANUARY 2017  
DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit  
FPD-Link II Serializer and Deserializer  
1 Features  
2 Applications  
1
•
5-MHz to 35-MHz Clock Embedded and DC-  
Balancing 24:1 and 1:24 Data Transmissions  
•
•
•
•
Automotive Central Information Displays  
Automotive Instrument Cluster Displays  
Automotive Heads-Up Displays  
•
User Defined Pre-Emphasis Driving Ability  
Through External Resistor on LVDS Outputs and  
Capable to Drive Up to 10-Meter Shielded  
Twisted-Pair Cable  
Remote Camera-Based Driver Assistance  
Systems  
•
•
User-Selectable Clock Edge for Parallel Data on  
Both Transmitter and Receiver  
3 Description  
The DS90C241 and DS90C124 chipset translates a  
24-bit parallel bus into a fully transparent data and  
control LVDS serial stream with embedded clock  
information. This single serial stream simplifies  
transferring a 24-bit bus over PCB traces or over  
cable by eliminating the skew problems between  
parallel data and clock paths. It saves system cost by  
narrowing data paths, which in turn reduces PCB  
layers, cable width, and connector size and pins.  
Internal DC Balancing Encode and Decode  
(Supports AC-Coupling Interface With No External  
Coding Required)  
•
•
Individual Power-Down Controls for Both  
Transmitter and Receiver  
Embedded Clock CDR (Clock and Data Recovery)  
on Receiver and No External Source of Reference  
Clock Required  
The DS90C241 and DS90C124 incorporate LVDS  
signaling on the high-speed I/O. LVDS provides a  
low-power and low-noise environment for reliably  
transferring data over a serial transmission path. By  
optimizing the serializer output edge rate for the  
operating frequency range, EMI is further reduced.  
•
•
•
•
•
•
All Codes RDL (Random Data Lock) to Support  
Live-Pluggable Applications  
LOCK Output Flag to Ensure Data Integrity at  
Receiver Side  
Balanced TSETUP and THOLD Between RCLK and  
RDATA on Receiver Side  
In addition, the device features pre-emphasis to boost  
signals over longer distances using lossy cables.  
Internal DC balanced encoding and decoding  
supports AC-coupled interconnects.  
PTO (Progressive Turnon) LVCMOS Outputs to  
Reduce EMI and Minimize SSO Effects  
All LVCMOS Inputs and Control Pins Have  
Internal Pulldown  
Device Information(1)  
On-Chip Filters for PLLs on Transmitter and  
Receiver  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
DS90C124  
DS90C241  
TQFP (48)  
7.00 mm x 7.00 mm  
•
•
•
•
•
Temperature Range: –40°C to 105°C  
Greater Than 8-kV HBM ESD Tolerant  
Meets AEC-Q100 Compliance  
Power Supply Range: 3.3 V ± 10%  
48-Pin TQFP Package  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Block Diagram  
PRE  
DEN  
VODSEL  
REN  
D
OUT  
+
R
+
IN  
24  
24  
R
D
OUT  
IN  
R -  
IN  
D
OUT  
-
TRFB  
TCLK  
Timing  
and  
Control  
PLL  
PLL  
LOCK  
RCLK  
RRFB  
RPWDNB  
Timing  
and  
Clock  
Recovery  
TPWDNB  
Control  
SERIALIZER œ DS90C241  
DESERIALIZER œ DS90C124  
Copyright © 2017, Texas Instruments Incorporated  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
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中文翻译

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DS90C124IVSX/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS90C124IVS/NOPB TI

完全替代

 5MHz 至 35MHz 直流平衡 24 位 FPD-Link II 解串器 | PFB

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DS90C124-Q1 TI

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 		5MHz 至 35MHz 直流平衡 24 位汽车类 FPD-Link II 解串器
DS90C124QVS NSC

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 		5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS90C124QVS/NOPB TI

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 		5MHz 至 35MHz 直流平衡 24 位汽车类 FPD-Link II 解串器 | P
DS90C124QVSX NSC

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 		5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS90C124QVSX/NOPB TI

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 		5MHz 至 35MHz 直流平衡 24 位汽车类 FPD-Link II 解串器 | P
DS90C185 TI

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 		Low Power 1.8V FPD-Link (LVDS) Serializer
DS90C185SQ/NOPB TI

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 		低功耗 FPD 链接 (LVDS) 串行器 | NJV | 48 | -10 to 70
DS90C185SQE/NOPB TI

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 		低功耗 FPD 链接 (LVDS) 串行器 | NJV | 48 | -10 to 70
DS90C185SQE-NOPB TI

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 		Low Power 1.8V FPD-Link (LVDS) Serializer
DS90C185SQ-NOPB TI

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 		Low Power 1.8V FPD-Link (LVDS) Serializer

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