Datasheet > DS567

DS567

更新时间： 2024-11-13 03:30:35

品牌	Logo	应用领域
赛灵思 - XILINX		内存控制器双倍数据速率 PC
页数	文件大小	规格书
24页	669K
描述
DDR2 Memory Controller for PowerPC 440 Processors

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DS567 数据手册

DDR2 Memory Controller for

PowerPC 440 Processors

DS567 (v1.1.1) March 31, 2008

Introduction

Reference Design Facts

This data sheet describes the DDR2 Memory Controller

Reference Design Specifics

reference design for the PowerPC

440 block

Supported Device

Virtex-5 FXT Platform FPGAs

Family

embedded in the Virtex™-5 FXT Platform FPGAs. It

interfaces with the Memory Controller Interface (MCI)

and provides the control interface for DDR2 memory.

Version of Reference

PPC440MC

v1_01_a

Design

Resources Used

Features

LUTs

See Table 9

•

Supports a maximum performance of 333 MHz in

the fastest speed grade

FFs

See Table 9

None

Block RAMs

Special Features

Supports 16-bit, 32-bit, and 64-bit data widths, and

72-bit data width with ECC (DQ:DQS = 8:1)

Provided with Reference Design

Supports DDR2 SDRAM single-rank registered

DIMMs and components

Documentation

Product Specification

Verilog

Design File Formats

Constraints File

Verification

Supports the following DDR2 SDRAM features:

UCF – in EDK PCORE directory

Verilog Testbench

♦

CAS latencies (3, 4, 5)

Additive latencies (0, 1, 2, 3, 4)

On-die termination (ODT)

Burst lengths (4, 8)

Instantiation Template Verilog Wrapper

Design Tool Requirements

Xilinx Implementation

ISE™ 10.1 SP1 or later

Tools

•

Supports bank management (up to four banks

open)

Verification

Simulation

Synthesis

ModelSim SE/EE 6.0c or later

XST

Performs the memory device initialization

sequence upon power-up

Performs auto-refresh cycles

Support

See "Notice of Disclaimer."

IBM Corp. and used under license. All other trademarks are the property of their respective owners.

DS567 (v1.1.1) March 31, 2008

www.xilinx.com

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