DS42514
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL163D Bottom Boot 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
SOFTWARE FEATURES
MCP Features
■ Power supply voltage of 2.7 to 3.3 volt
■ Data Management Software (DMS)
—
AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
Eases sector erase limitations
■ High performance
—
85 ns maximum access time
—
■ Package
■ Supports Common Flash Memory Interface (CFI)
■ Erase Suspend/Erase Resume
—
69-Ball FBGA
■ Operating Temperature
—
Suspends erase operations to allow programming in same
bank
—
–25°C to +85°C
■ Data# Polling and Toggle Bits
Flash Memory Features
—
Provides a software method of detecting the status of
program or erase cycles
ARCHITECTURAL ADVANTAGES
■ Unlock Bypass Program command
■ Simultaneous Read/Write operations
—
Reduces overall programming time when issuing multiple
program command sequences
—
Data can be continuously read from one bank while
executing erase/program functions in other bank
Zero latency between read and write operations
—
HARDWARE FEATURES
■ Secured Silicon (SecSi) Sector: Extra 64 KByte sector
■ Any combination of sectors can be erased
—
Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
■ Ready/Busy# output (RY/BY#)
—
Hardware method for detecting program or erase cycle
completion
—
Customer lockable: Can be read, programmed, or erased
just like other sectors. Once locked, data cannot be changed
■ Hardware reset pin (RESET#)
—
Hardware method of resetting the internal state machine to
reading array data
■ Zero Power Operation
Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero
—
■ WP#/ACC input pin
—
Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
■ Bottom boot block
■ Manufactured on 0.23 µm process technology
—
Acceleration (ACC) function accelerates program timing
■ Compatible with JEDEC standards
■ Sector protection
—
Pinout and software compatible with single-power-supply
flash standard
—
Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
PERFORMANCE CHARACTERISTICS
—
Temporary Sector Unprotect allows changing data in
protected sectors in-system
■ High performance
—
—
85 ns access time
Program time: 7 µs/word typical utilizing Accelerate function
SRAM Features
■ Power dissipation
■ Ultra low power consumption (typical values)
—
—
—
2 mA active read current at 1 MHz
—
—
Operating: 50 mA maximum
Standby: 7 µA maximum
10 mA active read current at 5 MHz
200 nA in standby or automatic sleep mode
■ CE1#s and CE2s Chip Select
■ Minimum 1 million write cycles guaranteed per sector
■ 20 Year data retention at 125°C
■ Power down features using CE1#s and CE2s
■ Data retention supply voltage: 1.5 to 3.3 volt
■ Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)
—
Reliable operation for the life of the system
Publication# 23756 Rev: B Amendment/2
Issue Date: March 15, 2001
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
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