Datasheet > DS42585

DS42585

更新时间： 2024-11-25 23:14:43

品牌	Logo	应用领域
超微 - AMD		闪存静态存储器
页数	文件大小	规格书
58页	905K
描述
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

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DS42585 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LFBGA, BGA73,10X12,32
针数：	73	Reach Compliance Code：	unknown
风险等级：	5.77	最长访问时间：	85 ns
其他特性：	SRAM IS ORGANISED AS 1M X 8 OR 512K X 16	JESD-30 代码：	R-PBGA-B73
JESD-609代码：	e0	长度：	11.6 mm
内存密度：	33554432 bit	内存集成电路类型：	MEMORY CIRCUIT
内存宽度：	16	混合内存类型：	FLASH+SRAM
功能数量：	1	端子数量：	73
字数：	2097152 words	字数代码：	2000000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-25 °C	组织：	2MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装等效代码：	BGA73,10X12,32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	子类别：	Other Memory ICs
最大压摆率：	0.045 mA	最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	8 mm	Base Number Matches：	1

DS42585 数据手册

PRELIMINARY

DS42585

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

Am29DL324D Bottom Boot 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only,

Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM

DISTINCTIVE CHARACTERISTICS

SOFTWARE FEATURES

MCP Features

■ Power supply voltage of 2.7 to 3.3 volt

■ Data Management Software (DMS)

—

AMD-supplied software manages data programming and

erasing, enabling EEPROM emulation

Eases sector erase limitations

■ High performance

—

85 ns maximum access time

—

■ Package

■ Supports Common Flash Memory Interface (CFI)

■ Erase Suspend/Erase Resume

—

73-Ball FBGA

■ Operating Temperature

—

Suspends erase operations to allow programming in same

bank

—

–25°C to +85°C

■ Data# Polling and Toggle Bits

Flash Memory Features

—

Provides a software method of detecting the status of

program or erase cycles

ARCHITECTURAL ADVANTAGES

■ Unlock Bypass Program command

■ Simultaneous Read/Write operations

—

Reduces overall programming time when issuing multiple

program command sequences

—

Data can be continuously read from one bank while

executing erase/program functions in other bank

Zero latency between read and write operations

—

HARDWARE FEATURES

■ Secured Silicon (SecSi) Sector: Extra 64 KByte sector

■ Any combination of sectors can be erased

—

Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable

as factory locked through autoselect function.

■ Ready/Busy# output (RY/BY#)

—

Hardware method for detecting program or erase cycle

completion

—

Customer lockable: Can be read, programmed, or erased

just like other sectors. Once locked, data cannot be changed

■ Hardware reset pin (RESET#)

—

Hardware method of resetting the internal state machine to

reading array data

■ Zero Power Operation

Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero

—

■ WP#/ACC input pin

—

Write protect (WP#) function allows protection of two outermost

boot sectors, regardless of sector protect status

■ Bottom boot block

■ Manufactured on 0.23 µm process technology

—

Acceleration (ACC) function accelerates program timing

■ Compatible with JEDEC standards

■ Sector protection

—

Pinout and software compatible with single-power-supply

flash standard

—

Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program or

erase operation within that sector

PERFORMANCE CHARACTERISTICS

—

Temporary Sector Unprotect allows changing data in

protected sectors in-system

■ High performance

—

Access time as fast 70 ns

Program time: 7 µs/word typical utilizing Accelerate function

SRAM Features

■ Power dissipation

■ Ultra low power consumption (typical values)

—

2 mA active read current at 1 MHz

—

Operating: 50 mA maximum

Standby: 7 µA maximum

10 mA active read current at 5 MHz

200 nA in standby or automatic sleep mode

■ CE1s# and CE2s Chip Select

■ Minimum 1 million write cycles guaranteed per sector

■ 20 Year data retention at 125°C

■ Power down features using CE1s# and CE2s

■ Data retention supply voltage: 1.5 to 3.3 volt

■ Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)

—

Reliable operation for the life of the system

Publication# 25032 Rev: A Amendment/0

Issue Date: May 22, 2001

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

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