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DS36277TM PDF预览

DS36277TM

更新时间: 2024-01-11 18:43:38
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动器接口集成电路光电二极管PC
页数 文件大小 规格书
12页 273K
描述
Dominant Mode Multipoint Transceiver

DS36277TM 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP8,.3针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.43
其他特性:COMMON I/O; 1 RECEIVER ACTIVE UNDER SHUTDOWN; TRISTATABLE RECEIVER差分输出:YES
驱动器位数:1高电平输入电流最大值:0.00002 A
输入特性:DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型:LINE TRANSCEIVER
接口标准:V.11; EIA-422-A; TIA-422-A; EIA-485; TIA-485JESD-30 代码:R-PDIP-T8
JESD-609代码:e3长度:9.817 mm
湿度敏感等级:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C最小输出摆幅:1.3 V
最大输出低电流:0.016 A输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
最大接收延迟:90 ns接收器位数:1
座面最大高度:5.08 mm子类别:Line Driver or Receivers
最大压摆率:75 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:NO技术:BIPOLAR
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
最大传输延迟:60 ns宽度:7.62 mm
Base Number Matches:1

DS36277TM 数据手册

 浏览型号DS36277TM的Datasheet PDF文件第2页浏览型号DS36277TM的Datasheet PDF文件第3页浏览型号DS36277TM的Datasheet PDF文件第4页浏览型号DS36277TM的Datasheet PDF文件第5页浏览型号DS36277TM的Datasheet PDF文件第6页浏览型号DS36277TM的Datasheet PDF文件第7页 
July 1998  
DS36277  
Dominant Mode Multipoint Transceiver  
General Description  
Features  
n FAILSAFE receiver, RO = HIGH for:  
— OPEN inputs  
The DS36277 Dominant Mode Multipoint Transceiver is de-  
signed for use on bi-directional differential busses. It is opti-  
mal for use on Interfaces that utilize Society of Automotive  
Engineers (SAE) J1708 Electrical Standard.  
Terminated inputs  
— SHORTED inputs  
n Optimal for use in SAE J1708 Interfaces  
n Compatible with popular interface standards:  
— TIA/EIA-485 and TIA/EIA-422-A  
— CCITT recommendation V.11  
n Bi-directional transceiver  
— Designed for multipoint transmission  
n Wide bus common mode range  
— (−7V to +12V)  
The device is similar to standard TIA/EIA-485 transceivers,  
but differs in enabling scheme. The Driver’s Input is normally  
externally tied LOW, thus providing only two states: Active  
(LOW), or Disabled (OFF). When the driver is active, the  
dominant mode is LOW, conversely, when the driver is dis-  
abled, the bus is pulled HIGH by external bias resistors.  
The receiver provides a FAILSAFE feature that guarantees a  
known output state when the Interface is in the following con-  
ditions: Floating Line, Idle Line (no active drivers), and Line  
Fault Conditions (open or short). The receiver output is  
HIGH for the following conditions: Open Inputs, Terminated  
Inputs (50), or Shorted Inputs. FAILSAFE is a highly desir-  
able feature when the transceivers are used with Asynchro-  
nous Controllers such as UARTs.  
n Available in plastic DIP and SOIC packages  
Connection and Logic Diagram  
Truth Tables  
Driver  
Inputs  
Outputs  
DE  
L
DI  
L
DO/RI  
DO /RI  
L
H
Z
H
L
L
H
X
H
Z
DS011384-1  
Order Number DS36277TM or DS36277TN  
See NS Package Number M08A or N08E  
Receiver  
Inputs  
Output  
RE  
L
DO/RI–DO /RI  
RO  
H
0 mV  
−500 mV  
SHORTED  
OPEN  
L
L
L
H
L
H
H
X
Z
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1999 National Semiconductor Corporation  
DS011384  
www.national.com  

DS36277TM 替代型号

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