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DS36277TN/NOPB PDF预览

DS36277TN/NOPB

更新时间: 2024-02-29 23:20:07
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
18页 1019K
描述
LINE TRANSCEIVER, PDIP8, PLASTIC, DIP-8

DS36277TN/NOPB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:8
Reach Compliance Code:unknown风险等级:5.62
其他特性:COMMON I/O; 1 RECEIVER ACTIVE UNDER SHUTDOWN; TRISTATABLE RECEIVER差分输出:YES
驱动器位数:1输入特性:DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型:LINE TRANSCEIVER接口标准:V.11; EIA-422-A; TIA-422-A; EIA-485; TIA-485
JESD-30 代码:R-PDIP-T8JESD-609代码:e3
长度:9.817 mm湿度敏感等级:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):260最大接收延迟:90 ns
接收器位数:1座面最大高度:5.08 mm
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:NO
技术:BIPOLAR温度等级:INDUSTRIAL
端子面层:TIN端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40最大传输延迟:60 ns
宽度:7.62 mm

DS36277TN/NOPB 数据手册

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DS36277  
www.ti.com  
SNLS086E JULY 1998REVISED APRIL 2013  
Dominant Mode Multipoint Transceiver  
Check for Samples: DS36277  
1
FEATURES  
DESCRIPTION  
The DS36277 Dominant Mode Multipoint Transceiver  
is designed for use on bi-directional differential  
busses. It is optimal for use on Interfaces that utilize  
Society of Automotive Engineers (SAE) J1708  
Electrical Standard.  
2
FAILSAFE Receiver, RO = HIGH for:  
OPEN Inputs  
Terminated Inputs  
SHORTED Inputs  
Optimal for Use in SAE J1708 Interfaces  
The device is similar to standard TIA/EIA-485  
transceivers, but differs in enabling scheme. The  
Driver's Input is normally externally tied LOW, thus  
providing only two states: Active (LOW), or Disabled  
(OFF). When the driver is active, the dominant mode  
is LOW, conversely, when the driver is disabled, the  
bus is pulled HIGH by external bias resistors.  
Compatible with Popular Interface Standards:  
TIA/EIA-485 and TIA/EIA-422-A  
CCITT Recommendation V.11  
Bi-Directional Transceiver  
Designed for Multipoint Transmission  
Wide Bus Common Mode Range  
(7V to +12V)  
Available in PDIP and SOIC Packages  
The receiver provides a FAILSAFE feature that  
ensures a known output state when the Interface is in  
the following conditions: Floating Line, Idle Line (no  
active drivers), and Line Fault Conditions (open or  
short). The receiver output is HIGH for the following  
conditions: Open Inputs, Terminated Inputs (50Ω), or  
Shorted Inputs. FAILSAFE is a highly desirable  
feature when the transceivers are used with  
Asynchronous Controllers such as UARTs.  
Connection and Logic Diagram  
See Package Number D (R-PDSO-G8)  
or  
P (R-PDIP-T8)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1998–2013, Texas Instruments Incorporated  

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