DS3141

更新时间： 2024-02-23 16:56:19

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
88页	1068K
描述
Single/Dual/Triple/Quad DS3/E3 Framers

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技术参数
数据手册

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DS3141 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	BGA,	针数：	144
Reach Compliance Code：	unknown	风险等级：	5.9
JESD-30 代码：	S-PBGA-B144	长度：	13 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	240
认证状态：	COMMERCIAL	座面最大高度：	1.75 mm
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	FRAMER	温度等级：	INDUSTRIAL
端子面层：	NOT SPECIFIED	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	13 mm

DS3141 数据手册

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

3. MAIN FEATURES

General

HDLC Controller

Cꢀ₍L_PIU_OSIn_/t_Ne_Erf_Gac_/Ces_LKca₎n_orb_Be_inE_ait_rh_ye₍r_DD_Au_Ta_/l_C-R_La_Ki_/l_LCV)

CꢀD_Me_ins_ii_mgn_ae_ld_Hoto_stH_Pa_rn_od_cl_ee_sM_sou_rlt_Ii_np_tle_erL_veA_nP_tD_ionMessages with

Cꢀ2_E5_n6_o-_uB_gy_hte_toR_Hec_ae_ni_dv_le_ea_thn_ed_TT_hra_ren_esm_Di_St ₃FI_PF_MO_Ds _Lar_Me_eL_sa_sr_ag_ge_es

CꢀSupport Gapped 52MHz Clock Rates

CꢀOptional B3ZS/HDB3 Encoder and Decoder

CꢀC_All_lo_oc_wk,_aD_Ga_lt_ua_e, _la_en_sd_sC_Ino_ten_rt_fr_ao_cl_eS_tig_on_Oa_tls_hec_ra_Dn_eb_ve_icI_en_sverted to

CꢀD_Ree_cte_ec_ivti_eon_Co_lof_cL_koss-of-Transmit Clock and Loss-of-

CꢀM_Pea_rn_fou_ra_ml o_ar_ncA_eut_Mom_ona_itt_oic_riO_ngne_C-S_oue_nc_to_en_rsd Update of

Cꢀ_MEa_oc_dh_eF_Wra_hm_ener_Nc_oa_tn_Bb_ee_inP_gu_Ut _sIn_et_do Low-Power Standby

(Path ID, Idle Signal ID, and Test Signal ID) that are

Sent and Received Once per Second

CꢀH_Sta_un_ffd_inle_gs_/DA_ell_st_th_ue_ffiN_ngo_,rm_Ca_Rl_CLa_ay_ne_dr_A2_bT_oa_rtsk_Gs_eS_neu_rc_ah_tiA_ons_/Zero

Checking, Flag Generation/Detection, and Byte

Alignment

Cꢀ_TP_rr_ao_ng_sra_mm_itm_aa_nb_dle_ReH_cig_eh_ivean_Fd_IFL_Oow_sWatermarks for the

Cꢀ_CTe_-Brm_iti_Pna_at_re_its_yt_mhe_odP_ea_ath_ndM_Oai_pn_tt_ie_on_na_an_llc_ye_thD_ea_Sta_n-L_Bin_itk_inin_ED₃S3

Receive Framer

Mode

CꢀF_anra_dm_Ge_.7S₅y₁nc_Eh₃ronization for M23 DS3, C-Bit Parity DS3,

FEAC Controller

Cꢀ_MDe_ins_ii_mgn_ae_ld_Hoto_stH_Pa_rn_od_cl_ee_sM_sou_rlt_Ii_np_tle_erF_veE_nA_tC_ionCodewords with

CꢀOptional B3ZS/HDB3 Decoding

CꢀDetects RAI, AIS, and DS3 Idle Signal

Cꢀ_LD_ie_nt_ee_-c_Cts_oda_end_ViA_oc_lac_tu_iom_nu_sla_(Cte_Vs_sB_),ip_Eo_xl_ca_er_sV_si_io_vl_eat_Zio_en_rs_os(B_(EP_XV_Z),_),

CꢀR_Coe_dce_ei_wve_orF_dE_sA_aC_ndA_Su_tt_oo_rm_esat_Tic_ha_ell_my V_inal_aid₄a_-t_Bes_ytI_enc_Fo_IFm_Oing

CꢀT_Cr_oa_dn_es_wm_oit_rdF_,E_OA_nC_ec_Ca_on_db_ee_woC_ro_dn_Cfig_ou_nr_te_ind_uoto_uS_sle_y,nd_orO_Tn_we_o

F-Bit Errors, M-Bit Errors, FAS Errors, P-Bit Parity

Errors, CP-Bit Parity Errors, and Far-End Block Errors

(FEBE)

Different Codewords Back-to-Back to Send DS3 Line

CꢀD_See_vte_ec_ret L_lyo_Ess_rr-_oo_rf_e-S_dig_Fn_raa_ml (_eLO_ES_ve),_nO_{t (}u_St-_Eo_Ff-₎F_,r_Cam_hae_n(_gO_eO_-oF_f-),

Loopback Commands

CꢀT_Me_or_dm_ein_aa_nt_des_Ot_ph_te_ioF_nE_alA_lyC_thC_eh_San_nn_Be_il_ti_in_nD_ES₃3_MC_o-_dB_eit Parity

Frame Alignment (COFA), Receipt of B3ZS/HDB3

Codewords, and DS3 Application ID Status

CꢀE_Bi3_t,N_tha_etio_Hn_Da_Ll _CBit_C(_oS_nn_t)_rois_lleF_ro_,r_aw_na_drd_the_ed_Fto_EAa_CSt_Cat_ou_ns_trR_ole_leg_rister

BERT

CꢀG₂enerates and Detects Pseudorandom Patterns

¹⁵- 1, 2²⁰- 1 (QRSS), 2²³- 1, and 2³¹- 1 as well as

Repetitive Patterns from 1 to 32 Bits in Length

Cꢀ_OSu_np_lyp_oo_rrt_Fs_uP_lla_Btte_ar_nn_dwIn_is_de_thrtion/Extraction in Either Payload

Cꢀ_fL_oa_rrg_Le_on2_g4-_PB_eit_riE_odrr_so_Wr C_ito_hu_on_ut_te_Hr _oA_sll_to_Pw_rs_ocT_ee_ss_sti_on_rg_Into_teP_rvr_eo_nce_tie_ond

Transmit Formatter

Cꢀ_GFr_.a₇m₅₁e_EIn₃sertion for M23 DS3, C-Bit Parity DS3, and

CꢀOptional B3ZS/HDB3 Encoding

CꢀClear-Channel Formatter Pass-Through Mode

CꢀGenerate RAI, AIS, and DS3 Idle Signals

CꢀAutomatic or Manual FEBE Insertion

Cꢀ_PEr_ar_to_ters_rnc_sa_fn_orbe_DiI_an_gs_ne_ort_se_td_icin_Puth_rpe_oG_see_sne_(Sra_inte_gd_leB_BE_itR_ET_{rrors or}

Specific Bit-Error Rates)

CꢀS_Eu_xcp_ep_so_sr_it_vA_eu_Zto_em_roa_st_,ic_F-o_Br_iM_{t E}a_rn_ru_oa_rsl_,In_Ms_-e_Br_it_tio_En_rro_of_rsB_,P_FV_As_S, CVs,

Loopback

CꢀDiagnostic Loopback (Transmit to Receive)

CꢀLine Loopback (Receive to Transmit)

CꢀPayload Loopback

Errors, P-Bit Parity Errors, and CP-Bit Parity Errors

Cꢀ_RE3_egN_isa_tt_eio_r,n_ta_hl_eB_Hit_D(S_Ln_C)_Cca_on_ntb_roe_llS_ero_,u_or_rce_thd_efr_Fo_Em_ACa C_Co_on_nt_tr_ro_ol_ller

Cꢀ_OAn_vy_erO_ridve_dr_eh_ne_ia_nd_thB_eit_TP_ro_as_ni_sti_mon_itc_Fa_on_rmbe_atE_tex_rte_Ur_sn_ia_nl_gly_the

Transmit Overhead Enable (TOHEN) and the Transmit

Overhead Input (TOH). This Feature Enables External

Control Over Unused Overhead Bits for Proprietary

Signaling Applications.

Microprocessor Interface

CꢀMultiplexed or Nonmultiplexed 8-Bit Processor Port

CꢀIntel and Motorola Bus Compatible

CꢀGlobal Reset-Input Pin

CꢀOptional Common Transmit Clock-Input Pin

CꢀGlobal Interrupt-Output Pin

7 of 88

1...4 5 678 9 10...88

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与DS3141相关器件

型号	品牌	描述	获取价格	数据表
DS3141+	MAXIM	暂无描述	获取价格
DS31412	MAXIM	6-/8-/12-Channel DS3/E3 Framers	获取价格
DS31412N	MAXIM	6-/8-/12-Channel DS3/E3 Framers	获取价格
DS31415	MAXIM	3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock	获取价格
DS31415	MICROCHIP	The DS31415 is a flexible, high-performance timing IC for diverse frequency conversion and	获取价格
DS31415_1107	MAXIM	3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock	获取价格

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