DS31407
List of Figures
Figure 2-1. Typical Application Example ..................................................................................................................... 7
Figure 3-1. DS31407 Block Diagram........................................................................................................................... 7
Figure 7-1. Input Clock Block Diagram...................................................................................................................... 15
Figure 7-2. DPLL Block Diagram............................................................................................................................... 20
Figure 7-3. DPLL State Transition Diagram .............................................................................................................. 21
Figure 7-4. APLL Block Diagram ............................................................................................................................... 30
Figure 7-5. FSYNC 8kHz Options.............................................................................................................................. 33
Figure 7-6. Embedded Sync in Output Clocks, Functional Timing............................................................................ 34
Figure 7-7. Embedded Sync in Output Clocks, One PWM Cycle.............................................................................. 34
Figure 7-8. Embedded Sync in Output Clocks, Three PWM Cycles ......................................................................... 34
Figure 7-9. Embedded Sync in Input Clocks, One PWM Cycle ................................................................................ 38
Figure 7-10. Embedded Sync in Input Clocks, Three PWM Cycles.......................................................................... 38
Figure 7-11. SPI Clock Phase Options...................................................................................................................... 40
Figure 7-12. SPI Bus Transactions............................................................................................................................ 41
Figure 9-1. JTAG Block Diagram............................................................................................................................. 101
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 103
Figure 10-1. Recommended External Components for Interfacing to Differential Inputs........................................ 107
Figure 10-2. Recommended External Components for Interfacing to CML Outputs............................................... 108
Figure 10-3. Recommended External Components for Interfacing to LVDS/LVPECL Outputs.............................. 109
Figure 10-4. SPI Interface Timing Diagram ............................................................................................................. 112
Figure 10-5. JTAG Timing Diagram......................................................................................................................... 113
Figure 11-1. Pin Assignment Diagram—Left Half.................................................................................................... 115
Figure 11-2. Pin Assignment Diagram—Right Half ................................................................................................. 116
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