DS31407
Table of Contents
1.
2.
3.
4.
5.
STANDARDS ................................................................................................................................ 6
APPLICATION EXAMPLE ............................................................................................................ 7
BLOCK DIAGRAM........................................................................................................................ 7
DETAILED DESCRIPTION............................................................................................................ 8
DETAILED FEATURES................................................................................................................. 9
5.1 INPUT CLOCK FEATURES .............................................................................................................. 9
5.2 DPLL FEATURES.......................................................................................................................... 9
5.3 DIGITAL FREQUENCY SYNTHESIZER FEATURES .............................................................................. 9
5.4 OUTPUT APLL FEATURES............................................................................................................. 9
5.5 OUTPUT CLOCK FEATURES......................................................................................................... 10
5.6 GENERAL FEATURES .................................................................................................................. 10
6.
7.
PIN DESCRIPTIONS................................................................................................................... 11
FUNCTIONAL DESCRIPTION .................................................................................................... 14
7.1 OVERVIEW ................................................................................................................................. 14
7.2 DEVICE IDENTIFICATION AND PROTECTION................................................................................... 14
7.3 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION........................................................... 14
7.3.1
Oscillator Characteristics to Minimize Output Jitter ............................................................................. 14
7.4 INPUT CLOCK CONFIGURATION.................................................................................................... 15
7.4.1
7.4.2
Signal Format Configuration ................................................................................................................ 15
Frequency Dividers, Scaling and Inversion.......................................................................................... 15
7.5 INPUT CLOCK MONITORING......................................................................................................... 16
7.5.1
7.5.2
7.5.3
Frequency Monitoring .......................................................................................................................... 16
Activity Monitoring................................................................................................................................ 17
Selected Reference Fast Activity Monitoring ....................................................................................... 18
7.6 INPUT CLOCK PRIORITY, SELECTION AND SWITCHING ................................................................... 18
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
Priority Configuration............................................................................................................................ 18
Automatic Selection ............................................................................................................................. 19
Forced Selection .................................................................................................................................. 19
Ultra-Fast Reference Switching ........................................................................................................... 19
External Reference Switching Mode.................................................................................................... 20
Output Clock Phase Continuity During Reference Switching .............................................................. 20
7.7 DPLL ARCHITECTURE AND CONFIGURATION ................................................................................ 20
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
DPLL State Machine ............................................................................................................................ 21
Bandwidth ............................................................................................................................................ 24
Damping Factor.................................................................................................................................... 24
Phase Detectors................................................................................................................................... 25
Loss of Phase Lock Detection ............................................................................................................. 26
Phase Monitor and Phase Build-Out.................................................................................................... 26
Manual Phase Adjustment ................................................................................................................... 27
Phase Recalibration............................................................................................................................. 28
Frequency and Phase Measurement................................................................................................... 28
7.7.10 Input Wander and Jitter Tolerance....................................................................................................... 28
7.7.11 Jitter and Wander Transfer .................................................................................................................. 28
7.7.12 Output Jitter and Wander..................................................................................................................... 29
7.7.13 ±160ppm Tracking Range Mode.......................................................................................................... 29
7.8 OUTPUT CLOCK CONFIGURATION ................................................................................................ 29
7.8.1
7.8.2
7.8.3
Enable and Interfacing ......................................................................................................................... 29
Frequency Configuration...................................................................................................................... 30
Phase Adjustment................................................................................................................................ 33
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