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DS2482S-101+T&R PDF预览

DS2482S-101+T&R

更新时间： 2024-02-23 08:21:12
品牌 Logo 应用领域
美信 - MAXIM 控制器
页数 文件大小 规格书
24页 345K
描述
Buffer/Inverter Based Peripheral Driver, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8

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DS2482S-101+T&R 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：SOIC包装说明：SOP,
针数：8Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.07其他特性：ALSO OPERATES AT 5V SUPPLY
内置保护：OVER CURRENT接口集成电路类型：BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码：R-PDSO-G8长度：4.9 mm
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出电流流向：SOURCE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压：5.5 V最小供电电压：2.9 V
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

DS2482S-101+T&R 数据手册

 浏览型号DS2482S-101+T&R的Datasheet PDF文件第2页浏览型号DS2482S-101+T&R的Datasheet PDF文件第3页浏览型号DS2482S-101+T&R的Datasheet PDF文件第4页浏览型号DS2482S-101+T&R的Datasheet PDF文件第6页浏览型号DS2482S-101+T&R的Datasheet PDF文件第7页浏览型号DS2482S-101+T&R的Datasheet PDF文件第8页 
Single-Channel 1-Wire Master with Sleep Mode  
DS482-01  
Pin Description  
PIN  
NAME  
FUNCTION  
SO  
1
WLP  
B3  
V
CC  
Power-Supply Input  
2
C3  
IO  
Input/Output Driver for 1-Wire Line  
3
C2  
GND  
SCL  
SDA  
Ground Reference  
2
4
B1  
I C Serial Clock Input. Must be connected to V through a pullup resistor.  
CC  
2
5
B2  
I C Serial Data Input/Output. Must be connected to V through a pullup resistor.  
CC  
Active-Low Control Output for an External p-Channel MOSFET. Provides extra power to the 1-Wire  
line, e.g., for use with 1-Wire devices that require a higher current temporarily to operate.  
6
A1  
PCTLZ  
Active-Low Control Input to Activate Low-Power Sleep Mode. This pin should be driven by a  
push-pull port.  
7
8
A2  
A3  
SLPZ  
AD0  
2
I C Address Input. Must be connected to V or GND.  
CC  
CONFIGURATION  
T-TIME OSC  
REGISTER  
INPUT/OUTPUT  
CONTROLLER  
LINE  
XCVR  
2
IO  
I C  
SDA  
INTERFACE  
SCL  
CONTROLLER  
PCTLZ  
STATUS  
REGISTER  
AD0  
SLPZ  
DS2482-101  
READ DATA  
REGISTER  
Figure 1. Block Diagram  
time-critical 1-Wire communication functions such as  
reset/presence-detect cycle, read-byte, write-byte, sin-  
gle-bit R/W, and triplet for ROM Search, without requir-  
ing interaction with the host processor. The host obtains  
feedback (completion of a 1-Wire function, presence  
pulse, 1-Wire short, search direction taken) through the  
Status Register and data through the Read Data  
Register. The DS2482-101 communicates with a host  
Detailed Description  
The DS2482-101 is a self-timed 1-Wire master that sup-  
ports advanced 1-Wire waveform features including  
standard and overdrive speeds, active pullup, and  
strong pullup for power delivery. The active pullup  
affects rising edges on the 1-Wire side. The strong  
pullup function uses the same pullup transistor as the  
active pullup, but with a different control algorithm. In  
addition, the strong pullup activates the PCTLZ pin,  
controlling optional external circuitry to deliver addition-  
al power beyond the capabilities of the on-chip pullup  
transistor. Once supplied with command and data, the  
input/output controller of the DS2482-101 performs  
2
processor through its I C bus interface in standard  
mode or in fast mode. The logic state of the address  
2
pin determines the I C slave address of the  
DS2482-101, allowing two devices operating on the  
same bus segment without requiring a hub. See  
Figure 1 for a block diagram.  
_______________________________________________________________________________________  
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