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DS2482S-100/T&R PDF预览

DS2482S-100/T&R

更新时间： 2024-01-20 17:37:59
品牌 Logo 应用领域
美信 - MAXIM 控制器
页数 文件大小 规格书
24页 350K
描述
Buffer/Inverter Based Peripheral Driver, PDSO8, 0.150 INCH, SOP-8

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DS2482S-100/T&R 技术参数

生命周期：Active包装说明：SOP,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.56
其他特性：ALSO OPERATES WITH 2.9 TO 3.7 V接口集成电路类型：BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出电流流向：SOURCE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE座面最大高度：1.75 mm
最大供电电压：5.5 V最小供电电压：2.9 V
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL断开时间：2.2 µs
宽度：3.9 mmBase Number Matches：1

DS2482S-100/T&R 数据手册

 浏览型号DS2482S-100/T&R的Datasheet PDF文件第1页浏览型号DS2482S-100/T&R的Datasheet PDF文件第2页浏览型号DS2482S-100/T&R的Datasheet PDF文件第3页浏览型号DS2482S-100/T&R的Datasheet PDF文件第5页浏览型号DS2482S-100/T&R的Datasheet PDF文件第6页浏览型号DS2482S-100/T&R的Datasheet PDF文件第7页 
Single-Channel 1-Wire Master  
ELECTRICAL CHARACTERISTICS (continued)  
(V  
CC  
= 2.9V to 5.5V, T = -40°C to +85°C.)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
0
TYP  
MAX  
10  
UNITS  
pF  
Input Capacitance  
C
(Note 9)  
I
SCL Clock Frequency  
f
400  
kHz  
SCL  
Hold Time (Repeated) START  
Condition (After this period, the  
first clock pulse is generated.)  
t
0.6  
μs  
HD:STA  
Low Period of the SCL Clock  
High Period of the SCL Clock  
t
1.3  
0.6  
μs  
μs  
LOW  
DS482-10  
t
HIGH  
Setup Time for a Repeated  
START Condition  
t
0.6  
μs  
SU:STA  
Data Hold Time  
t
t
t
(Notes 11, 12)  
(Note 13)  
0.9  
μs  
ns  
μs  
HD:DAT  
SU:DAT  
SU:STO  
Data Setup Time  
250  
0.6  
Setup Time for STOP Condition  
Bus Free Time Between a STOP  
and START Condition  
t
1.3  
μs  
BUF  
Capacitive Load for Each Bus  
Line  
C
(Note 14)  
(Note 15)  
400  
100  
pF  
μs  
B
Oscillator Warmup Time  
t
OSCWUP  
Note 1: Operating current with 1-Wire write-byte sequence followed by continuously reading the Status Register at 400kHz in overdrive.  
Note 2: With standard speed, the total capacitive load of the 1-Wire bus should not exceed 1nF. Otherwise, the passive pullup on  
threshold V may not be reached in the available time. With overdrive speed, the capacitive load on the 1-Wire bus must  
IL1  
not exceed 300pF.  
Note 3: Active pullup guaranteed to turn on between V  
and V  
.
IH1(MIN)  
IL1(MAX)  
Note 4: Active or resistive pullup choice is configurable.  
Note 5: Except for t , all 1-Wire timing specifications and t  
are derived from the same timing circuit. Therefore, if one of  
APUOT  
F1  
these parameters is found to be off the typical value, it is safe to assume that all these parameters deviate from their typi-  
cal value in the same direction and by the same degree.  
Note 6: These values apply at full load, i.e., 1nF at standard speed and 0.3nF at overdrive speed. For reduced load, the pulldown  
slew rate is slightly faster.  
Note 7: Fall time high-to-low (t ) is derived from PD  
, referenced from 0.9 x V  
to 0.1 x V  
.
F1  
SRC  
CC  
CC  
2
Note 8: All I C timing values are referred to V  
and V  
levels.  
IH(MIN)  
IL(MAX)  
Note 9: Applies to SDA, SCL, AD0 and AD1.  
Note 10: The input/output pins of the DS2482-100 do not obstruct the SDA and SCL lines if V  
is switched off.  
CC  
Note 11: The DS2482-100 provides a hold time of at least 300ns for the SDA signal (referred to the V  
of the SCL signal) to  
IH(MIN)  
bridge the undefined region of the falling edge of SCL.  
Note 12: The maximum t  
need only be met if the device does not stretch the low period (t  
) of the SCL signal.  
LOW  
HD:DAT  
2
2
Note 13: A fast-mode I C bus device can be used in a standard-mode I C bus system, but the requirement t  
≥ 250ns must  
SU:DAT  
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device  
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t  
250 = 1250ns (according to the standard-mode I C bus specification) before the SCL line is released.  
+ t  
= 1000 +  
R(MAX)  
SU:DAT  
2
2
Note 14: C —Total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall times according to I C-  
B
Bus Specification Version 2.1 are allowed.  
Note 15: I C communication should not take place for the max t  
2
time following a power-on reset.  
OSCWUP  
4
_______________________________________________________________________________________  
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