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DS2482-800_V01 PDF预览

DS2482-800_V01

更新时间: 2022-06-24 15:44:39
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
23页 321K
描述
8-Channel 1-Wire Master

DS2482-800_V01 数据手册

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DS2482-800: 8-Channel 1-Wire Master  
PARAMETER  
Write 0 Low Time  
SYMBOL  
CONDITIONS  
Standard  
MIN  
TYP  
MAX  
UNITS  
60  
7.1  
64  
7.5  
5.3  
3.0  
600  
72  
68  
7.9  
tW0L  
µs  
Overdrive  
Standard  
Overdrive  
Standard  
Overdrive  
Standard  
Overdrive  
Standard  
Overdrive  
Standard  
Overdrive  
5.0  
5.6  
Write 0 Recovery Time  
Reset Low Time  
tREC0  
tRSTL  
tMSP  
tSI  
µs  
µs  
µs  
µs  
µs  
2.8  
3.2  
570  
68.4  
66.5  
7.1  
630  
75.6  
73.5  
7.9  
70  
Presence-Detect Sample Time  
7.5  
8
7.6  
8.4  
Sampling for Short and  
Interrupt  
0.7  
0.75  
584  
74  
0.8  
554.8  
70.3  
613.2  
77.7  
Reset High Time  
tRSTH  
I2C-Pins (Note 7) See Figure 9  
0.25 ×  
VCC  
0.22 ×  
VCC  
V
CC = 2.9V to 3.7V  
LOW Level Input Voltage  
VIL  
-0.5  
V
VCC = 4.5V to 5.5V  
0.7 ×  
VCC  
0.05 ×  
VCC  
VCC +  
0.5V  
HIGH Level Input Voltage  
VIH  
Vhys  
VOL  
V
V
V
Hysteresis of Schmitt Trigger  
Inputs  
LOW Level Output Voltage at  
3mA Sink Current  
Output Fall Time from VIhmin to  
VILmax with a Bus Capacitance  
from 10pF to 400pF  
Pulse Width of Spikes that are  
Suppressed by the Input Filter  
Input Current Each I/O Pin with  
an Input Voltage Between  
0.1VCCmax and 0.9VCCmax  
Input Capacitance  
0.4  
250  
50  
tof  
tSP  
Ii  
60  
ns  
ns  
µA  
SDA and SCL pins only  
(Notes 8, 9)  
(Note 8)  
-10  
+10  
Ci  
10  
pF  
SCL Clock Frequency  
fSCL  
0
400  
kHz  
Hold Time (Repeated) START  
Condition. After this Period, the  
First Clock Pulse is Generated.  
LOW Period of the SCL Clock  
HIGH Period of the SCL Clock  
Setup Time for a Repeated  
START Condition  
tHD:STA  
0.6  
µs  
tLOW  
tHIGH  
1.3  
0.6  
µs  
µs  
tSU:STA  
0.6  
µs  
Data Hold Time  
Data Setup Time  
tHD:DAT  
tSU:DAT  
tSU:STO  
(Notes 10, 11)  
(Note 12)  
0.9  
µs  
ns  
µs  
250  
0.6  
Setup Time for STOP Condition  
Bus Free Time Between a  
STOP and START Condition  
Capacitive Load for Each Bus  
Line  
tBUF  
1.3  
µs  
Cb  
(Note 13)  
(Note 14)  
400  
100  
pF  
µs  
Oscillator Warm-Up Time  
tOSCWUP  
3 of 23  

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