Single-Channel 1-Wire Master with Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.9V to 5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Current Each Input/Output
Pin with an Input Voltage
I
(Notes 11, 12)
(Note 11)
-10
+10
μA
I
Between 0.1 x V
and
CC(MAX)
0.9 x V
CC(MAX)
Input Capacitance
C
10
pF
I
SCL Clock Frequency
f
0
400
kHz
SCL
DS482-01
Hold Time (Repeated) START
Condition (After this period, the
first clock pulse is generated.)
t
t
0.6
μs
HD:STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
1.3
0.6
μs
μs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
0.6
μs
SU:STA
Data Hold Time
t
t
t
(Notes 13, 14)
(Note 15)
0.9
μs
ns
μs
HD:DAT
SU:DAT
SU:STO
Data Setup Time
250
0.6
Setup Time for STOP Condition
Bus Free Time Between a STOP
and START Condition
t
1.3
μs
BUF
Capacitive Load for Each Bus
Line
C
(Note 16)
(Note 8)
400
100
pF
μs
B
Oscillator Warmup Time
t
OSCWUP
Note 1: Operating current with 1-Wire write-byte sequence followed by continuously reading the Status Register at 400kHz in overdrive.
Note 2: With standard speed, the total capacitive load of the 1-Wire bus should not exceed 1nF. Otherwise, the passive pullup on
threshold V may not be reached in the available time. With overdrive speed, the capacitive load on the 1-Wire bus must
IL1
not exceed 300pF.
Note 3: Active pullup guaranteed to turn on between V
and V
.
IH1(MIN)
IL1(MAX)
Note 4: Active or resistive pullup choice is configurable.
Note 5: Except for t , all 1-Wire timing specifications and t
are derived from the same timing circuit. Therefore, if one of
APUOT
F1
these parameters is found to be off the typical value, it is safe to assume that all these parameters deviate from their typi-
cal value in the same direction and by the same degree.
Note 6: These values apply at full load, i.e., 1nF at standard speed and 0.3nF at overdrive speed. For reduced load, the pulldown
slew rate is slightly faster.
Note 7: Fall time high-to-low (t ) is derived from PD
Note 8: I C communication should not take place for the max t
, referenced from 0.9 x V
to 0.1 x V
.
F1
SRC
CC
CC
2
or t
time following a power-on reset or a wakeup from
OSCWUP
SWUP
sleep mode.
Note 9: Guaranteed by design and not production tested.
2
Note 10: All I C timing values are referred to V
Note 11: Applies to SDA, SCL, and AD0.
and V
levels.
IL(MAX)
IH(MIN)
Note 12: The input/output pins of the DS2482-101 do not obstruct the SDA and SCL lines if V
Note 13: The DS2482-101 provides a hold time of at least 300ns for the SDA signal (referred to the V
is switched off.
CC
of the SCL signal) to
IH(MIN)
bridge the undefined region of the falling edge of SCL.
Note 14: The maximum t
need only be met if the device does not stretch the low period (t
) of the SCL signal.
LOW
HD:DAT
2
2
Note 15: A fast-mode I C bus device can be used in a standard-mode I C bus system, but the requirement t
≥ 250ns must
SU:DAT
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
250 = 1250ns (according to the standard-mode I C bus specification) before the SCL line is released.
+ t
= 1000 +
R(MAX)
SU:DAT
2
2
Note 16: C —Total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall times according to I C-
B
Bus Specification Version 2.1 are allowed.
4
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