DS2480

更新时间： 2024-02-22 16:45:04

品牌	Logo	应用领域
达拉斯 - DALLAS		驱动器
页数	文件大小	规格书
26页	189K
描述
Serial 1.Wire Line Driver

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技术参数
数据手册

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DS2480 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP, SOP8,.25
针数：	8	Reach Compliance Code：	not_compliant
风险等级：	5.87	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	湿度敏感等级：	1
端子数量：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	5 V	认证状态：	Not Qualified
子类别：	Serial IO/Communication Controllers	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL

DS2480 数据手册

DS2480

+ 5 TO 12V RS232 OPTO ISOLATED Figure 10e

POWER

SUPPLY

POWER

STEALING

12V

REGULATOR

DTR

RTS

RXD

1.5 k

HCPL–2202

POL

1–W

5.1 k

1–WIRE BUS

UART

RXD

DS2480

TXD

OR µC

TXD

2.7 k

GND

HCPL–2300

1µ

GND

RETURN

START

STOP

The circuit in Figure 10e combines the true RS232C

interface with opto–isolation. The energy to power the

LED in the TXD channel and to provide the positive volt-

age for the host’s RXD input is stolen from DTR and

RTS. The negative voltage for the RXD input is taken

from the TXD line through a parasitic supply consisting

of a Schottky diode in series with a capacitor. The

HCPL–2202 opto–isolator has a totem pole output that

allows switching in positive as well as negative voltage.

The +5V are sufficient for most RS232C systems.

Switching in 12V requires a opto–isolator with different

voltage characteristics.

In the schematic the HCPL–2202 opto–isolator is

sourced by the RXD pin of the DS2480. It can as well be

connected the traditional way where the DS2480 sinks

the current through the LED. This, however, causes a

signalinversionthathastobecompensatedthroughthe

DS2480byusingavaluecodeof100,101,110or111for

the RS232 baud rate setting. Using other types of opto–

isolators than shown in the schematic will at least

require changing the values of the resistors.

RS232 DATA TIMING RXD LINE Figure 11

START

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

STOP

IDLER

(DIAGRAM DRAWN FOR POL = 5V)

10 T

RECEIVE DELAY TIMING Figure 12

BIT 6

BIT 7

STOP

(DIAGRAM DRAWN FOR POL = 5V)

START BIT 0

TXD

RESP

RXD

INPUT SAMPLING 8.5T

9.5T

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