Datasheet > DS2408S/T&R

DS2408S/T&R

更新时间： 2024-02-22 08:05:09

品牌	Logo	应用领域
美信 - MAXIM		光电二极管外围集成电路
页数	文件大小	规格书
36页	539K
描述
Parallel I/O Port, 8 I/O, CMOS, PDSO16, 0.150 INCH, SOP-16

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技术参数
数据手册

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DS2408S/T&R 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	0.150 INCH, SOP-16
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.36	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	长度：	9.9 mm
I/O 线路数量：	8	端口数量：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	245
认证状态：	Not Qualified	座面最大高度：	1.75 mm
最大供电电压：	5.25 V	最小供电电压：	2.8 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3.9 mm
uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE	Base Number Matches：	1

DS2408S/T&R 数据手册

DS2408

Conditional Search Channel Selection Mask Register

The data in this register controls whether a PIO channel qualifies for participation in the conditional

search command. To include one or more of the PIO channels, the bits in this register that correspond to

those channels need to be set to 1. This register can only be written through the Write Conditional Search

Registers command.

Conditional Search Channel Selection Mask Register Bitmap

ADDR

008Bh

SM7

SM6

SM5

SM4

SM3

SM2

SM1

SM0

This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7.

This register is cleared to 00h by a power-on reset

Conditional Search Channel Polarity Selection Register

The data in this register specifies the polarity of each selected PIO channel for the device to respond to

the conditional search command. Within a PIO channel, the data source may be either the channel's input

signal (pin) or the channel's activity latch, as specified by the PLS bit in the Control/Status register at ad-

dress 008Dh. This register can only be written through the Write Conditional Search Registers command.

Conditional Search Channel Polarity Selection Register Bitmap

ADDR

008Ch

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7.

This register is cleared to 00h by a power-on reset.

Figure 7. Conditional Search Logic

PLS

SP0

SM0

CHANNEL 0

AL0

INPUT FROM

CHANNELS 1 TO 6

(NOT SHOWN)

CSR

CHANNEL 7

SP7

SM7

AL7

10 of 36

1...7 8 91011 12 13...36

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