Datasheet > DS2176Q

DS2176Q

更新时间： 2024-02-04 18:19:37

品牌	Logo	应用领域
美信 - MAXIM		电信电信集成电路
页数	文件大小	规格书
15页	305K
描述
Elastic Buffer, CMOS, PQCC28, PLASTIC, LCC-28

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DS2176Q 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	PLASTIC, LCC-28	针数：	28
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.28
运营商类型：	CEPT PCM-30/E-1	运营商类型（2）：	T-1(DS1)
数据速率：	2048 Mbps	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e0	长度：	11.505 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC28,.5SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	245	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	4.57 mm
子类别：	Digital Transmission Interfaces	最大压摆率：	0.01 mA
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ELASTIC BUFFER
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	11.505 mm	Base Number Matches：	1

DS2176Q 数据手册

DS2176

OVERVIEW

The DS2176 performs two primary functions: 1) synchronization of received T1 PCM data (looped

timed) to host backplane frequencies; 2) supervision of robbed–bit signaling data embedded in the data

stream. The buffer, while optimized for use with the DS2180A T1 Transceiver, is also compatible with

other transceiver devices. The DS2180A data sheet should serve as a valuable reference when designing

with the DS2176.

RECEIVE SIDE TIMING FIGURE 2

DATA SYNCHRONIZATION

PCM BUFFER

The DS2176 utilizes a 2–frame buffer (386 bits) to synchronize incoming PCM data to the system

backplane clock. The buffer samples data at RSER on the falling edge of RCLK. Output data appears at

SSER and is up-dated on the rising edge of SYSCLK. A rising edge at RMSYNC establishes receive side

frame and multi-frame alignment. A rising edge at SFSYNC establishes system side frame alignment.

The buffer depth is constantly monitored by onboard contention logic; a “slip” occurs when the buffer is

completely emptied or filled. Slips automatically recenter the buffer to a one–frame depth and always

occur on frame boundaries.

SLIP CORRECTION CAPABILITY

The 2–frame buffer depth is adequate for most T–carrier applications where short–term jitter

synchronization, rather than correction of significant frequency differences, is required. The DS2176

provides an ideal balance between total delay and slip correction capability.

BUFFER RECENTERING

Many applications require that the buffer be recentered during system power–up and/or initialization.

Forcing ALN low recenters the buffer on the occurrence of the next frame sync boundary. A slip will

occur during this recentering if the buffer depth is adjusted. If the depth is presently optimum, no

adjustment (slip) occurs. SLIP is held low for 65 SYSCLK cycles when a slip occurs. SLIP is an active–

low, open collector output.

BUFFER DEPTH MONITORING

SMSYNC is a system side output pulse which indicates system side multiframe boundaries. The distance

between rising edges at RMSYNC and SMSYNC indicates the current buffer depth. Slip direction and/or

an impending slip condition may be determined by monitoring RMSYNC and SMSYNC real time.

SMSYNC is held high for 65 SYSCLK cycles.

CLOCK SELECT

The device is compatible with two common backplane frequencies: 1.544 MHz, selected when

SCLKSEL=0; and 2.048 MHz, selected when SCLKSEL=1. In 1.544 MHz applications the F–bit is

4 of 15

1 2 345 6 7...15

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DS2176Q 替代型号

型号	品牌	替代类型	描述	数据表
DS2176QN/T&R	MAXIM	完全替代	Elastic Buffer, CMOS, PQCC28, PLASTIC, LCC-28

与DS2176Q相关器件

型号	品牌	描述	获取价格	数据表
DS2176Q/T&R	MAXIM	Elastic Buffer, CMOS, PQCC28, PLASTIC, LCC-28	获取价格
DS2176Q+	MAXIM	Elastic Buffer, CMOS, PQCC28, ROHS COMPLIANT, PLASTIC, LCC-28	获取价格
DS2176QIND	ETC	Telecommunication IC	获取价格
DS2176QN	ETC	PCM Receiver	获取价格
DS2176QN/T&R	MAXIM	Elastic Buffer, CMOS, PQCC28, PLASTIC, LCC-28	获取价格
DS218	ETC	Analog IC	获取价格

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