DS2174
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TABLE OF CONTENTS
1.
GENERAL OPERATION ................................................................................................................4
1.1 PATTERN GENERATION......................................................................................................................4
1.1.1 Polynomial Generation..........................................................................................4
1.1.2 Repetitive Pattern Generation ...............................................................................4
1.2 PATTERN SYNCHRONIZATION............................................................................................................5
1.2.1 Synchronization......................................................................................................5
1.2.2 Polynomial Synchronization ..................................................................................5
1.2.3 Repetitive Pattern Synchronization .......................................................................5
1.3 BIT ERROR RATE (BER) CALCULATION............................................................................................5
1.3.1 Counters.................................................................................................................5
1.4 GENERATING ERRORS .......................................................................................................................5
1.5 CLOCK DISCUSSION...........................................................................................................................6
1.6 POWER-UP SEQUENCE.......................................................................................................................6
1.7 DETAILED PIN DESCRIPTION .............................................................................................................8
PARALLEL CONTROL INTERFACE........................................................................................10
CONTROL REGISTERS ...............................................................................................................11
3.1 MODE SELECT .................................................................................................................................13
2.
3.
3.1.1 Error Insertion.....................................................................................................13
3.2 STATUS REGISTER ...........................................................................................................................15
3.3 PSEUDORANDOM PATTERN REGISTERS ...........................................................................................15
3.4 TEST REGISTER................................................................................................................................17
3.5 COUNT REGISTERS ..........................................................................................................................17
RAM ACCESS.................................................................................................................................18
4.1 INDIRECT ADDRESSING....................................................................................................................18
DC OPERATION ............................................................................................................................19
AC TIMING CHARACTERISTICS .............................................................................................20
6.1 PARALLEL PORT ..............................................................................................................................20
6.2 DATA INTERFACE ............................................................................................................................22
MECHANICAL DIMENSIONS ....................................................................................................24
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