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DS2174QN+T&R PDF预览

DS2174QN+T&R

更新时间: 2024-01-09 06:20:49
品牌 Logo 应用领域
美信 - MAXIM 电信电信集成电路
页数 文件大小 规格书
24页 265K
描述
Telecom Circuit, 1-Func, PQCC44, PLASTIC, LCC-44

DS2174QN+T&R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ, LDCC44,.7SQ针数:44
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.68JESD-30 代码:S-PQCC-J44
JESD-609代码:e3长度:16.585 mm
湿度敏感等级:3功能数量:1
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Other Telecom ICs最大压摆率:0.06 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:16.585 mm
Base Number Matches:1

DS2174QN+T&R 数据手册

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DS2174  
1.5 Clock Discussion  
There are two methods for moving test patterns through a telecom network.  
1) The clock applied to TCLK and RCLK can be gapped by other devices on the target system. The  
gapped clock would be applied to TCLK and RCLK only during the appropriate times. TDATn  
outputs remain active during clock gaps.  
2) The clock applied to TCLK and RCLK can be continuous at the applicable line rate and the  
TCLK_EN and RCLK_EN pins can be asserted and deasserted during the appropriate time slots.  
TDATn outputs remain active even when TCLK_EN is pulled low. The output level remains static at  
the level of the last bit transmitted (output high for a 1, output low for a 0).  
1.6 Power-Up Sequence  
On power-up, the registers in the DS2174 are in a random state. The user must program all the internal  
registers to a known state before proper operation can be ensured.  
Figure 1-1. Block Diagram  
CR1.5  
LC  
BIT COUNTER  
ERROR COUNTER  
RCLK_EN  
RECEIVE  
PATTERN DETECTOR  
SYNC  
RATE  
RCLK  
CONTROL  
RDAT[7:0]  
CR1.0  
TL  
2n - 1  
TCLK_EN  
TRANSMIT  
RATE  
TCLK  
TDAT[7:0]  
ERROR INSERTION  
CONTROL  
REPETITIVE PATTERN  
GENERATOR  
TCLK0  
PARALLEL CONTROL PORT  
WR A[3:0]  
CS RD  
D[7:0]  
6 of 24  

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