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DS1813R-10 PDF预览

DS1813R-10

更新时间: 2024-11-14 20:29:23
品牌 Logo 应用领域
达拉斯 - DALLAS 光电二极管
页数 文件大小 规格书
5页 41K
描述
Power Supply Support Circuit, Fixed, 1 Channel, +4.35VV, CMOS, PDSO3, SOT-23, 3 PIN

DS1813R-10 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:SOT-23, 3 PINReach Compliance Code:unknown
风险等级:5.68Is Samacsys:N
其他特性:Pushbutton Reset option可调阈值:NO
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUITJESD-30 代码:R-PDSO-G3
JESD-609代码:e0信道数量:1
功能数量:1端子数量:3
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装等效代码:TO-236
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:1.2/5.5 V认证状态:Not Qualified
子类别:Power Management Circuits最大供电电流 (Isup):0.05 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子位置:DUAL阈值电压标称:+4.35V
Base Number Matches:1

DS1813R-10 数据手册

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DS1813  
DS1813  
5V EconoReset with Pushbutton  
FEATURES  
PIN ASSIGNMENT  
Automatically restarts a microprocessor after power  
failure  
3
Monitors pushbutton for external override  
Maintains reset for typically 150 ms after V returns  
CC  
to an in–tolerance condition  
1
2
SOT–23 PACKAGE  
Reduces need for discrete components  
Precision temperature–compensated voltage  
reference and voltage sensor  
Low–cost TO–92 or space saving surface–mount  
SOT–23 packages available  
1
2
3
Efficient open–drain output with internal 5.5K  
pull–up resistor  
1
2
3
TO–92 PACKAGE  
See Mech. Drawings  
Section  
Operating temperature –40°C to +85°C  
PIN DESCRIPTIONS  
TO–92  
1
2
3
RST  
Active Low Reset Output  
Power Supply  
Ground  
V
CC  
GND  
SOT–23  
1
2
3
RST  
Active Low Reset Output  
Power Supply  
Ground  
V
GND  
CC  
DESCRIPTION  
The DS1813 EconoReset usesaprecisiontemperature  
referenceandcomparatorcircuittomonitorthestatusof  
naliskeptintheactivestateforapproximately150msto  
allow the power supply and processor to stabilize.  
the power supply (V ). When an out–of–tolerance  
condition is detected, an internal power–fail signal is  
generated which forces reset to the active state. When  
CC  
The DS1813 also monitors a pushbutton on the reset  
output. If the reset line is pulled low, a reset is generated  
upon release and will be held in reset output low for typi-  
cally 150 ms.  
V
CC  
returns to an in–tolerance condition, the reset sig-  
ECopyright 1995 by Dallas Semiconductor Corporation.  
All Rights Reserved. For important information regarding  
patents and other intellectual property rights, please refer to  
Dallas Semiconductor data books.  
082196 1/5  

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