Datasheet > DS1345YB-100-IND

DS1345YB-100-IND

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
美信 - MAXIM		电池静态存储器监控
页数	文件大小	规格书
12页	220K
描述
1024k Nonvolatile SRAM with Battery Monitor

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DS1345YB-100-IND 数据手册

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DS1345Y/AB

(t_A: See Note 10)

UNITS NOTES

POWER-DOWN/POWER-UP TIMING

PARAMETER

SYMBOL MIN

t_PD

t_F

t_RPD

t_R

TYP

MAX

1.5

µs

V_CCFail Detect to CE and WE Inactive

V_CCslew from V_TPto 0V

150

V_CCFail Detect to RST Active

V_CCslew from 0V to V_TP

t_PU

V_CCValid to CE and WE Inactive

V_CCValid to End of Write Protection

V_CCValid to RST Inactive

t_REC

t_RPU

t_BPU

125

350

150

200

V_CCValid to BW Valid

BATTERY WARNING TIMING

PARAMETER

(t_A: See Note 10)

SYMBOL MIN

TYP

MAX

UNITS NOTES

Battery Test Cycle

t_BTC

t_BTPW

t_BW

Battery Test Pulse Width

Battery Test to BW Active

(t_A= 25°C)

PARAMETER

SYMBOL MIN

TYP

MAX

UNITS NOTES

Expected Data Retention Time

t_DR

years

WARNING:

Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery

backup mode.

NOTES:

1. WE is high for a Read Cycle.

2. OE = V_IHor V_IL. If OE = V_IHduring write cycle, the output buffers remain in a high-impedance state.

3. t_WPis specified as the logical AND of CE and WE . t_WPis measured from the latter of CE or WE

going low to the earlier of CE or WE going high.

4. t_DSis measured from the earlier of CE or WE going high.

5. These parameters are sampled with a 5pF load and are not 100% tested.

6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output

buffers remain in a high-impedance state during this period.

7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output

buffers remain in high-impedance state during this period.

8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,

the output buffers remain in a high impedance state during this period.

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