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DS1088LU-27 PDF预览

DS1088LU-27

更新时间: 2024-11-09 14:37:51
品牌 Logo 应用领域
美信 - MAXIM 光电二极管外围集成电路
页数 文件大小 规格书
15页 198K
描述
Clock Generator, CMOS, PDSO8, MICRO, SOP-8

DS1088LU-27 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:TSSOP,
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.77
JESD-30 代码:S-PDSO-G8长度:3 mm
端子数量:8最高工作温度:85 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:1.1 mm最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

DS1088LU-27 数据手册

 浏览型号DS1088LU-27的Datasheet PDF文件第2页浏览型号DS1088LU-27的Datasheet PDF文件第3页浏览型号DS1088LU-27的Datasheet PDF文件第4页浏览型号DS1088LU-27的Datasheet PDF文件第5页浏览型号DS1088LU-27的Datasheet PDF文件第6页浏览型号DS1088LU-27的Datasheet PDF文件第7页 
DS1WM  
Synthesizable 1-Wire Bus Master  
www.maxim-ic.com  
FEATURES  
C Memory maps into any standard byte-wide  
data bus.  
Customer ASIC  
C Eliminates CPU “bit-banging” by internally  
generating all 1-Wire® timing and control  
signals.  
Internal  
1-Wire  
Bus  
1-Wire  
Master  
C Generates interrupts to provide for more  
efficient programming.  
Data Bus  
C Search ROM Accelerator relieves CPU from  
any single bit operations on the 1-Wire Bus.  
C Supports Overdrive mode and slave  
interrupts.  
Interrupt  
C Capable of running off any system clock from  
3.2MHz to 128MHz.  
C Small size: all digital design, only 1500 gates.  
C Available in both Verilog and VHDL.  
C Applications include any circuit containing a  
1-Wire communication bus.  
DESCRIPTION  
As more 1-Wire devices become available, more and more users have to deal with the demands of  
generating 1-Wire signals to communicate to them. This usually requires “bit-banging” a port pin on a  
microprocessor, and having the microprocessor perform the timing functions required for the 1-Wire  
protocol. While 1-Wire transmission can be interrupted mid-byte, it cannot be interrupted during the  
“low” time of a bit time slot; this means that a CPU will be idled for up to 60 microseconds for each bit  
sent and at least 480 microseconds when generating a 1-Wire reset. The 1-Wire Master helps users handle  
communication to 1-Wire devices in their system without tying up valuable CPU cycles. Integrated into a  
user’s ASIC as a 1-Wire port, the core is available in both VHDL and Verilog code and uses very little  
chip area (1492 gates plus 1 bond pad for the Verilog version).  
This circuit is designed to be memory mapped into the user’s system and provides complete control of the  
1-Wire bus through 8 bit commands. The host CPU loads commands, reads and writes data, and sets  
interrupt control through five individual registers. All of the timing and control of the 1-Wire bus are  
generated within. The host merely needs to load a command or data and then may go on about its  
business. When bus activity has generated a response that the CPU needs to receive, the 1-Wire Master  
sets a status bit and, if enabled, generates an interrupt to the CPU. In addition to write and read  
simplification, the 1-Wire Master also provides a Search ROM Accelerator function relieving the CPU  
from having to perform any single-bit operations on the 1-Wire bus.  
1-Wire is a registered trademark of Dallas Semiconductor.  
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031902  

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