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DS1085Z-25 PDF预览

DS1085Z-25

更新时间: 2024-02-23 15:32:16
品牌 Logo 应用领域
达拉斯 - DALLAS 信号电路锁相环或频率合成电路光电二极管
页数 文件大小 规格书
21页 332K
描述
EconOscillator Frequency Synthesizer

DS1085Z-25 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:2.27Samacsys Confidence:3
Samacsys Status:ReleasedSamacsys PartID:231946
Samacsys Pin Count:8Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline PackagesSamacsys Footprint Name:21-0041
Samacsys Released Date:2015-11-27 06:31:41Is Samacsys:N
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm湿度敏感等级:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:133 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

DS1085Z-25 数据手册

 浏览型号DS1085Z-25的Datasheet PDF文件第5页浏览型号DS1085Z-25的Datasheet PDF文件第6页浏览型号DS1085Z-25的Datasheet PDF文件第7页浏览型号DS1085Z-25的Datasheet PDF文件第9页浏览型号DS1085Z-25的Datasheet PDF文件第10页浏览型号DS1085Z-25的Datasheet PDF文件第11页 
DS1085  
Table 7a. PRESCALER P0 DIVISOR M SETTINGS  
0M1  
0M0  
PRESCALER P0  
DIVISOR “M”  
0
0
1
1
0
1
0
1
1*  
2
4
8
*Factory Default Setting  
Table 7b. PRESCALER P1 DIVISOR M SETTINGS  
1M1  
1M0  
PRESCALER P1  
DIVISOR “M”  
0
0
1
1
0
1
0
1
1*  
2
4
8
*Factory Default Setting  
NOTE:  
When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case for  
situations when OUT0 is not used. Under these conditions all the circuitry associated with OUT0 is  
powered down. OUT0 is powered down (see Table 2).  
PDN1 (Default Setting = 0)  
If PDN1 = 1, CTRL1 functions as a power-down (see Table 3).  
If PDN1 = 0, CTRL1 functions as an output enable for OUT1 (see Table 3).  
NOTES FOR OUTPUT ENABLE AND POWER-DOWN:  
1) Both enables are “smart” and wait for the output to be low before going to High-Z.  
2) A power-down sequence first disables both outputs before powering down the device.  
3) On power-up, the outputs are disabled until the clock has stabilized (~8000 cycles).  
4) In power-down mode the device cannot be programmed.  
5) A power-down command must persist for at least two cycles of the lowest output frequency plus  
10µs.  
DIV WORD (N) (Address 01h)  
MSB  
LSB MSB  
LSB  
X
N9 N8 N7 N6 N5 N4 N3 N2 N1 N0  
X
X
X
X
X
First Data Byte  
Second Data Byte  
X = Don’t care.  
8 of 21  

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