Datasheet > DS1077L

DS1077L

更新时间： 2023-12-20 18:45:03

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
21页	289K
描述
3V、EconOscillator/分频器

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数据手册

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DS1077L 数据手册

DS1077L

TABLE 3

PDN0

PDN1

SHUTDOWN CONTROL

(BIT)

None*

CTRL1

CTRL0

CTRL0 or CTRL1

*CTRL0 performs a power-down if SEL0 and EN0 are both 0. (See Table 1.)

Serial Data Input/Output (SDA) – Input/output pin for the 2-wire serial interface used for data transfer.

Serial Clock Input (SCL) – Input pin for the 2-wire serial interface used to synchronize data movement

on the serial interface.

The user-programmable registers can be programmed by the user to determine the mode of operation

(MUX), operating frequency (DIV) and bus settings (BUS). Details of how these registers are

programmed can be found in a later section; in this section the functions of the registers are described.

The register setting are nonvolatile, the values are stored automatically or as required in EEPROM when

the registers are programmed via the SDA and SCL pins.

MUX WORD

MSB

LSB MSB

LSB

PDN1 PDN0

SEL0 EN0 0M1

0M0

1M1

1M0

DIV1

Name

Default setting

first data byte

second data byte

*This bit must be set to zero.

DIV1 (bit)

This bit allows the output of the prescaler P1 to be routed directly to the OUT1 pin (DIV1 = 1). The N

divider is bypassed so the programmed value of N is ignored. If DIV1 = 0 (default) the N divider

functions normally.

0M1, 0M0, 1M1, 1M0 (bits)

These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8. (See Table 4.)

TABLE 4

PRESCALER

P1 DIVISOR

“M”

0M1

0M0

P0 DIVISOR 1M1 1M0

“M”

*Default Condition

5 of 21

1 2 3 456 7 8...21

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