Datasheet > DS1077L

DS1077L

更新时间： 2023-12-20 18:45:03

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
21页	289K
描述
3V、EconOscillator/分频器

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数据手册

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DS1077L 数据手册

DS1077L

TABLE 1

EN0

SEL0

(BIT)

PDN0

(BIT)

CTRL0

(PIN)

OUT0

(PIN)

CTRL0

DEVICE

(BIT)

FUNCTION

MODE

Hi-Z

Power-Down

(OUT1 and OUT2)

Power-Down*

Hi-Z

Active

Master Clk/M

Master Clk

Hi-Z

Master Clk

Hi-Z

MUX Select

Output Enable

Active

Active**

Master Clk/M

Hi-Z

Power-Down

(OUT1 and OUT2)

Master Clk

Power-Down

Active

Power-Down

Active

Hi-Z

Master Clk/M

Power-Down

*This mode is for applications where OUT0 is not used, but CTRL0 is used as a device shutdown.

**Default Condition

CONTROL PIN 1 (CTRL1) – A multifunctional input pin that can be selected as an output enable

and/or a power-down. Its function is determined by the user-programmable control register value of

PDN1. (See Table 2.)

TABLE 2

PDN1

(BIT)

CTRL1

(PIN)

CTRL1

OUT 1

Out Clk

Hi-Z

DEVICE MODE

Active*

FUNCTION

Output Enable

Power-Down

Active*

Out Clk

Active

Hi-Z

Power-Down

(OUT1 and OUT2)

*Default Condition

NOTE:

Both CTRL0 and CTRL1 can be configured as power-downs, they are internally “OR” connected so that

either of the control pins may be used to provide a power-down function for the whole device, subject to

appropriate settings of the PDN0 and PDN1 register bits. (See Table 3.)

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