5秒后页面跳转
DS1073M-80 PDF预览

DS1073M-80

更新时间: 2024-02-16 22:23:30
品牌 Logo 应用领域
达拉斯 - DALLAS /
页数 文件大小 规格书
18页 261K
描述
3V EconOscillator/Divider

DS1073M-80 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:8
Reach Compliance Code:unknown风险等级:5.68
JESD-30 代码:R-PDIP-T8JESD-609代码:e0
长度:9.375 mm湿度敏感等级:NOT SPECIFIED
端子数量:8最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):245
认证状态:COMMERCIAL座面最大高度:4.572 mm
最大供电电压:3.6 V最小供电电压:2.7 V
标称供电电压:3 V表面贴装:NO
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

DS1073M-80 数据手册

 浏览型号DS1073M-80的Datasheet PDF文件第4页浏览型号DS1073M-80的Datasheet PDF文件第5页浏览型号DS1073M-80的Datasheet PDF文件第6页浏览型号DS1073M-80的Datasheet PDF文件第8页浏览型号DS1073M-80的Datasheet PDF文件第9页浏览型号DS1073M-80的Datasheet PDF文件第10页 
DS1073  
Figure 6  
tM = PERIOD OF MCLK  
td = PROP DELAY FROM MCLK I TO OUT I  
tOUTH = WIDTH OF OUTPUT PULSE  
MAX VALUE OF tdis = tSUEM + td + tOUTH + tM  
MIN VALUE OF tdis = tSUEM + td + tOUTH  
SELECT TIMING  
If the PDN bit is set to 0, the PDN /SELX pin can be used to switch between the internal oscillator and an  
externalor crystal reference. The “Enabling Sequencer” is again employed to ensure this transition occurs  
in a glitch-free fashion. Two asynchronous clock signals are involved, INTCLK is the internal reference  
oscillator divided by one or whatever value of M is selected. EXTCLK is the clock signal fed into the  
OSCIN pin, or the clock resulting from a crystal connected between OSCIN and XTAL. The behavior of  
OUT0 is described in the following paragraphs, the OUT pin will behavior similarly but will be divided  
by N.  
FROM INTERNAL TO EXTERNAL CLOCK  
This is accomplished by a high to low transition on the SELX pin. This transition is detected on the  
falling edge of INTCLK. The output OUT0 will be held low for a minimum of half the period of  
INTCLK (tI/2), then if EXTCLK is low it will be routed through to OUT0. If EXTCLK is high the  
switching will not occur until EXTCLK returns to a low level.  
Figure 7  
Depending on the relative timing of the SELX signal and the internal clock, there may be up to one full  
cycle of tI on the output after the falling edge of SELX . Then, the “low” time (tLOW) between output  
pulses will be dependent on the relative timing between tI and tE. The time interval between the falling  
edge of SELX and the first rising edge of the externally derived clock is tSIE. Approximate maximum and  
minimum values of these parameters are:  
tLOW (min) = tI/2  
tLOW (max) = tI/2 + tE  
tSIE (min) = tI/2  
t
SIE (max) = 3tI/2 + tE  
NOTE:  
In each case there will be a small additional delay due to internal propagation delays.  
7 of 18  

与DS1073M-80相关器件

型号 品牌 描述 获取价格 数据表
DS1073-SPECIAL ETC Special EconOscillator/Divider

获取价格

DS1073Z-100 DALLAS 3V EconOscillator/Divider

获取价格

DS1073Z-100 MAXIM Microprocessor Circuit, CMOS, PDSO8, 0.150 INCH, SOIC-8

获取价格

DS1073Z-60 DALLAS 3V EconOscillator/Divider

获取价格

DS1073Z-60 MAXIM Microprocessor Circuit, CMOS, PDSO8, 0.150 INCH, SOIC-8

获取价格

DS1073Z-66 MAXIM Microprocessor Circuit, CMOS, PDSO8, 0.150 INCH, SOIC-8

获取价格