Datasheet > DS1073M-80

DS1073M-80

更新时间： 2024-02-13 14:00:02

品牌	Logo	应用领域
达拉斯 - DALLAS		/
页数	文件大小	规格书
18页	261K
描述
3V EconOscillator/Divider

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技术参数
数据手册

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DS1073M-80 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.68
JESD-30 代码：	R-PDIP-T8	JESD-609代码：	e0
长度：	9.375 mm	湿度敏感等级：	NOT SPECIFIED
端子数量：	8	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	245
认证状态：	COMMERCIAL	座面最大高度：	4.572 mm
最大供电电压：	3.6 V	最小供电电压：	2.7 V
标称供电电压：	3 V	表面贴装：	NO
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

DS1073M-80 数据手册

DS1073

Table 2

MSEL

DIV1

BIT

BIT*

BIT

OPERATION

INTERNAL OSCILLATOR DIVIDED BY 4*N

INTERNAL OSCILLATOR DIVIDED BY 2*N

INTERNAL OSCILLATOR DIVIDED BY N

EXTERNAL OSCILLATOR DIVIDED BY N

INTERNAL OSCILLATOR DIVIDED BY 1

INTERNAL OSCILLATOR DIVIDED BY 4

INTERNAL OSCILLATOR DIVIDED BY 2

EXTERNAL OSCILLATOR DIVIDED BY 1

*Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the PDN /SELX pin.

DIV WORD Figure 3

(MSB)

(LSB)

N (9-BITS)

PDN

This bit is used to determine the function of the PDN /SELX pin. If PDN = 0, the PDN /SELX pin can be

used to determine the timing reference (either the internal oscillator or an external reference/crystal). If

PDN = 1, the PDN /SELX pin is used to put the device into power-down mode.

EN0

This bit is used to determine whether the OUT0 pin is active or not. If EN0 = 1, OUT0 is disabled (High-

impedance). If EN0 = 0, the internal reference clock (MCLK) is output from OUT0. The OE pin has no

effect on OUT0, but OUT0 is disabled as part of the power-down sequence.

These nine bits determine the value of the programmable divider. The range of divisor values is from 2 to

513, and is equal to the programmed value of N plus 2:

Table 3

BIT

DIVISOR (N)

VALUES

VALUE

000000000

000000001

111111111

513

NOTE:

The maximum value of N is constrained by the minimum output frequency. If the internal clock is

selected, INTOSC/(M*N) must be greater than f_OUTmin; if the external clock is selected, EXTCLK/N must

be greater than f_OUTmin. (If DIV1 = 1, then INTOSC or EXTCLK, as applicable, must exceed f_OUTmin).

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1 2 3 456 7 8...18

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