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DS1005M-250 PDF预览

DS1005M-250

更新时间： 2024-11-21 04:39:07
品牌 Logo 应用领域
达拉斯 - DALLAS 延迟线
页数 文件大小 规格书
6页 65K
描述
5-Tap Silicon Delay Line

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中文翻译

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DS1005M-250 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：0.300 INCH, DIP-8Reach Compliance Code：unknown
风险等级：5.62其他特性：BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT
系列：CMOS/TTL输入频率最大值（fmax）：2.5 MHz
JESD-30 代码：R-PDIP-T8JESD-609代码：e0
逻辑集成电路类型：SILICON DELAY LINE功能数量：1
抽头/阶步数：5端子数量：8
最高工作温度：70 °C最低工作温度：
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP8,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5 V最大电源电流（ICC）：75 mA
可编程延迟线：NOProp。Delay @ Nom-Sup：250 ns
认证状态：Not Qualified子类别：Delay Lines
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
总延迟标称（td）：250 nsBase Number Matches：1

DS1005M-250 数据手册

 浏览型号DS1005M-250的Datasheet PDF文件第2页浏览型号DS1005M-250的Datasheet PDF文件第3页浏览型号DS1005M-250的Datasheet PDF文件第4页浏览型号DS1005M-250的Datasheet PDF文件第5页浏览型号DS1005M-250的Datasheet PDF文件第6页 
DS1005  
5-Tap Silicon Delay Line  
www.dalsemi.com  
FEATURES  
PIN ASSIGNMENT  
ꢀ All-silicon time delay  
IN  
1
2
14  
13  
VCC  
NC  
IN  
1
2
16  
15  
VCC  
NC  
ꢀ 5 taps equally spaced  
ꢀ Delay tolerance ±2 ns or ±3%, whichever is  
greater  
ꢀ Stable and precise over temperature and  
voltage range  
ꢀ Leading and trailing edge accuracy  
ꢀ Economical  
ꢀ Auto-insertable, low profile  
ꢀ Standard 14-pin DIP, 8-pin DIP, or 16-pin  
SOIC  
NC  
NC  
NC  
TAP 2  
NC  
3
4
5
6
7
12  
11  
10  
9
TAP 1  
NC  
NC  
TAP 2  
NC  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
NC  
TAP 1  
NC  
TAP 3  
NC  
TAP 3  
NC  
TAP 4  
GND  
TAP 4  
NC  
8
TAP 5  
GND  
TAP 5  
DS1005 14-Pin DIP (300-mil)  
See Mech. Drawings Section  
DS1005S 16-Pin SOIC  
(300-mil)  
See Mech. Drawings Section  
ꢀ Tape and reel available for surface-mount  
ꢀ Low-power CMOS  
ꢀ TTL/CMOS compatible  
ꢀ Vapor phase, IR and wave solderability  
ꢀ Custom delays available  
ꢀ Quick turn prototypes  
1
VCC  
8
IN  
2
7
TAP 1  
TAP 3  
TAP 5  
TAP 2  
TAP 4  
GND  
3
4
6
5
ꢀ Extended temperature range available  
DS1005M 8-Pin DIP (300-mil)  
See Mech. Drawings Section  
PIN DESCRIPTION  
TAP 1-TAP 5 - TAP Output Number  
VCC  
GND  
NC  
- +5 Volts  
- Ground  
- No Connection  
- Input  
IN  
DESCRIPTION  
The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns  
to 250 ns, with an accuracy of ±2 ns or ±3%, whichever is greater. This device is offered in a standard 14-  
pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin  
SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is  
achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC  
packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead  
configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by  
the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each  
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to  
meet special needs. For special requests and rapid delivery, call (972) 371–4348.  
1 of 6  
111799  
123456

中文翻译

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