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DP8459V-25 PDF预览

DP8459V-25

更新时间： 2024-11-23 22:17:47
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动电子器件驱动程序和接口接口集成电路
页数 文件大小 规格书
35页 406K
描述
All-Code Data Synchronizer

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中文翻译

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DP8459V-25 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCJ, LDCC28,.5SQReach Compliance Code：unknown
风险等级：5.82Is Samacsys：N
驱动类型：FLOPPY; OPTICAL; TAPE接口集成电路类型：DATA SYNCHRONIZER OR ENDEC
JESD-30 代码：S-PQCC-J28JESD-609代码：e0
长度：11.43 mm功能数量：1
端子数量：28最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Drive Electronics最大压摆率：190 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：BIPOLAR温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：11.43 mm
Base Number Matches：1

DP8459V-25 数据手册

 浏览型号DP8459V-25的Datasheet PDF文件第2页浏览型号DP8459V-25的Datasheet PDF文件第3页浏览型号DP8459V-25的Datasheet PDF文件第4页浏览型号DP8459V-25的Datasheet PDF文件第5页浏览型号DP8459V-25的Datasheet PDF文件第6页浏览型号DP8459V-25的Datasheet PDF文件第7页 
ADVANCED  
December 1995  
DP8459 All-Code Data Synchronizer  
PREAMBLE DETECTED signal when  
a pre-determined  
General Description  
length of the user-selected pattern is encountered. All digital  
input and output signals are TTL compatible and a single,  
+5V power supply is required. The DP8459V is offered as a  
DP8459V-10 (250 Kbit/sec thru 10 Mbits/sec) or  
DP8459V-25 (250 Kbits/sec thru 25 Mbit/sec), see AC  
Electrical Characteristics.  
The DP8459 Data Synchronizer is an integrated phase  
locked loop circuit which has been designed for application  
in magnetic hard disk, flexible (floppy) disk, optical disk, and  
tape drive memory systems for data re-synchronization and  
clock recovery with any standard recording code, operating  
to 25 Mb/s. The DP8459 is provided in a 28-pin PCC  
package. Zero phase start is employed during both data and  
reference clock lock sequences for rapid acquisition. An  
Features  
n Fully integrated dual-gain PLL  
optional  
(Customer-controlled)  
synchronization  
field  
n Zero phase start lock sequence  
frequency-acquisition feature guarantees lock, accommo-  
dating the preamble types used with GCR (Group Code  
Recording), MFM (Modified Frequency Modulation), the  
[1,N] run length limited (RLL) codes, and either of the  
standard 2,7 RLL codes. Precise synchronization window  
generation is achieved via an internal, self-aligning delay line  
which remains accurate independent of temperature, power  
supply, external component and IC process variations. The  
DP8459 also incorporates a digitally controlled ( MICROW-  
n 250 Kbit/sec–25 Mbit/sec data rate range  
n Frequency lock capability (optional) for all standard  
recording codes  
n Digital window strobe control, 5-bit resolution  
n Two-port PLL filter network  
n PLL free-run (Coast) control for optical disk defects  
n Synchronization pattern (preamble lock) detection  
n Non-glitching multiplexed read/write clock output  
n +5V supply  
n DP8459 supplied in 28-pin plastic chip carrier (PCC)  
and 40-pin TapePak packages  
™
IRE bus compatible) strobe function with 5-bit resolution  
which allows for margin testing, error recovery routines, and  
precise window calibration. The PLL filter resides external to  
the chip, with two ports provided to allow significant design  
flexibility. Synchronization pattern detection circuitry issues a  
Connection Diagrams  
TL/F/9322-6  
FIGURE 1. DP8459 in 28-Pin Plastic Chip Carrier (PCC) V-Type Package Order Number DP8459V-10 or DP8459V-25  
TapePak® is a registered trademark of National Semiconductor Corporation.  
™
MICROWIRE is a trademark of National Semiconductor Corporation.  
© 1996 National Semiconductor Corporation  
TL/F/9322  
http:\\www.national.com  
1
PrintDate=1996/07/31 PrintTime=11:05:38 ds009322 Rev. No. 1 Proof  
1
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DP8459V-25 替代型号

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