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DP8459V-25NS

更新时间： 2024-11-23 22:17:47

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
35页	406K
描述
All-Code Data Synchronizer

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中文翻译

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数据手册

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DP8459V-25NS 数据手册

ADVANCED

December 1995

DP8459 All-Code Data Synchronizer

PREAMBLE DETECTED signal when

a pre-determined

General Description

length of the user-selected pattern is encountered. All digital

input and output signals are TTL compatible and a single,

+5V power supply is required. The DP8459V is offered as a

DP8459V-10 (250 Kbit/sec thru 10 Mbits/sec) or

DP8459V-25 (250 Kbits/sec thru 25 Mbit/sec), see AC

Electrical Characteristics.

The DP8459 Data Synchronizer is an integrated phase

locked loop circuit which has been designed for application

in magnetic hard disk, ﬂexible (ﬂoppy) disk, optical disk, and

tape drive memory systems for data re-synchronization and

clock recovery with any standard recording code, operating

to 25 Mb/s. The DP8459 is provided in a 28-pin PCC

package. Zero phase start is employed during both data and

reference clock lock sequences for rapid acquisition. An

Features

n Fully integrated dual-gain PLL

optional

(Customer-controlled)

synchronization

ﬁeld

n Zero phase start lock sequence

frequency-acquisition feature guarantees lock, accommo-

dating the preamble types used with GCR (Group Code

Recording), MFM (Modiﬁed Frequency Modulation), the

[1,N] run length limited (RLL) codes, and either of the

standard 2,7 RLL codes. Precise synchronization window

generation is achieved via an internal, self-aligning delay line

which remains accurate independent of temperature, power

supply, external component and IC process variations. The

DP8459 also incorporates a digitally controlled ( MICROW-

n 250 Kbit/sec–25 Mbit/sec data rate range

n Frequency lock capability (optional) for all standard

recording codes

n Digital window strobe control, 5-bit resolution

n Two-port PLL ﬁlter network

n PLL free-run (Coast) control for optical disk defects

n Synchronization pattern (preamble lock) detection

n Non-glitching multiplexed read/write clock output

n +5V supply

n DP8459 supplied in 28-pin plastic chip carrier (PCC)

and 40-pin TapePak packages

™

IRE bus compatible) strobe function with 5-bit resolution

which allows for margin testing, error recovery routines, and

precise window calibration. The PLL ﬁlter resides external to

the chip, with two ports provided to allow signiﬁcant design

ﬂexibility. Synchronization pattern detection circuitry issues a

Connection Diagrams

TL/F/9322-6

FIGURE 1. DP8459 in 28-Pin Plastic Chip Carrier (PCC) V-Type Package Order Number DP8459V-10 or DP8459V-25

TapePak^®is a registered trademark of National Semiconductor Corporation.

™

MICROWIRE is a trademark of National Semiconductor Corporation.

TL/F/9322

http:\\www.national.com

PrintDate=1996/07/31 PrintTime=11:05:38 ds009322 Rev. No. 1 Proof

12 3 4 5 6 7...35

中文翻译

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DP84600MS4I	NSC	获取价格	4 CHANNEL READ WRITE AMPLIFIER CIRCUIT, PDSO20, SSOP-20
DP84600R	ETC	获取价格
DP84600RM4	NSC	获取价格	IC 4 CHANNEL READ WRITE AMPLIFIER CIRCUIT, PDSO20, PLASTIC, SOP-20, Drive Electronics
DP84600RM4I	NSC	获取价格	IC 4 CHANNEL READ WRITE AMPLIFIER CIRCUIT, PDSO20, PLASTIC, SOP-20, Drive Electronics
DP84600RMS4	NSC	获取价格	IC 4 CHANNEL READ WRITE AMPLIFIER CIRCUIT, PDSO20, SSOP-20, Drive Electronics

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