Datasheet > DP8420A

DP8420A

更新时间： 2024-11-22 23:16:31

品牌	Logo	应用领域
美国国家半导体 - NSC		驱动器内存控制器
页数	文件大小	规格书
58页	822K
描述
microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

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DP8420A 数据手册

July 1992

DP8420A/21A/22A microCMOS Programmable

256k/1M/4M Dynamic RAM Controller/Drivers

General Description

Features

On chip high precision delay line to guarantee critical

DRAM access timing parameters

The DP8420A/21A/22A dynamic RAM controllers provide a

low cost, single chip interface between dynamic RAM and

all 8-, 16- and 32-bit systems. The DP8420A/21A/22A gen-

erate all the required access control signal timing for

DRAMs. An on-chip refresh request clock is used to auto-

matically refresh the DRAM array. Refreshes and accesses

are arbitrated on chip. If necessary, a WAIT or DTACK out-

put inserts wait states into system access cycles, including

burst mode accesses. RAS low time during refreshes and

RAS precharge time after refreshes and back to back ac-

cesses are guaranteed through the insertion of wait states.

Separate on-chip precharge counters for each RAS output

can be used for memory interleaving to avoid delayed back

to back accesses because of precharge. An additional fea-

ture of the DP8422A is two access ports to simplify dual

accessing. Arbitration among these ports and refresh is

done on chip.

microCMOS process for low power

High capacitance drivers for RAS, CAS, WE and DRAM

address on chip

On chip support for nibble, page and static column

DRAMs

Byte enable signals on chip allow byte writing in a word

size up to 32 bits with no external logic

Selection of controller speeds: 20 MHz and 25 MHz

On board Port A/Port B (DP8422A only)/refresh arbitra-

tion logic

Direct interface to all major microprocessors (applica-

tion notes available)

4 RAS and 4 CAS drivers (the RAS and CAS configura-

tion is programmable)

Largest

DRAM

Direct Drive

Memory

Access

Ports

of Pins

of Address

Outputs

Control

(PLCC)

Possible

Capacity

Available

DP8420A

DP8421A

DP8422A

256 kbit

1 Mbit

4 Mbit

4 Mbytes

16 Mbytes

64 Mbytes

Single Access Port

Dual Access Ports (A and B)

Block Diagram

DP8420A/21A/22A DRAM Controller

TL/F/8588–5

FIGURE 1

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

Staggered Refresh^TMis a trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation

TL/F/8588

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7...58

中文翻译

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与DP8420A相关器件

型号	品牌	获取价格	描述	数据表
DP8420AV-20	NSC	获取价格	microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers
DP8420AV-20	ROCHESTER	获取价格	256K X 1, DRAM CONTROLLER, PQCC68, PLASTIC, LCC-68
DP8420AV-20X	NSC	获取价格	暂无描述
DP8420AV-25	NSC	获取价格	microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers
DP8420AV-25	ROCHESTER	获取价格	256K X 1, DRAM CONTROLLER, PQCC68, PLASTIC, LCC-68
DP8420V	NSC	获取价格	microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers
DP8420V-20	ETC	获取价格	DRAM Controller
DP8420V-25	ETC	获取价格	DRAM Controller
DP8420V-33	NSC	获取价格	microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers
DP8420V-33	ROCHESTER	获取价格	256K X 1, DRAM CONTROLLER, PQCC68, PLASTIC, LCC-68

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