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DP8392CN-1 PDF预览

DP8392CN-1

更新时间: 2024-01-20 07:17:10
品牌 Logo 应用领域
德州仪器 - TI 以太网:16GBASE-T电信光电二极管电信集成电路
页数 文件大小 规格书
14页 474K
描述
DATACOM, ETHERNET TRANSCEIVER, PDIP16, PLASTIC, DIP-16

DP8392CN-1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.85
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:19.305 mm负电源额定电压:-9 V
功能数量:1端子数量:16
收发器数量:1最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:-9 V
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Network Interfaces最大压摆率:0.18 mA
表面贴装:NO电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

DP8392CN-1 数据手册

 浏览型号DP8392CN-1的Datasheet PDF文件第1页浏览型号DP8392CN-1的Datasheet PDF文件第2页浏览型号DP8392CN-1的Datasheet PDF文件第4页浏览型号DP8392CN-1的Datasheet PDF文件第5页浏览型号DP8392CN-1的Datasheet PDF文件第6页浏览型号DP8392CN-1的Datasheet PDF文件第7页 
2.0 Block Diagram  
TL/F/11085–2  
FIGURE 1. DP8392C Block Diagr
3.0 Functional Description  
The CTI consists of four main logical blocks:  
Receiver n stays only if within about 1 ms, the DC  
level w pass ter rises above the DC squelch  
threllustrates the Receiver timing.  
a) the Receiver - receives data from the coax and sends it  
to the DTE  
Thriver provides ECL compatible signals  
to thcally 3 ns rise and fall times. In its idle  
state, to differential zero to prevent DC stand-  
ing current he isolation transformer.  
b) the Transmitter - accepts data from the DTE and trans-  
mits it onto the coax  
c) the Collision Detect circuitry - indicates to the DTE any  
collision on the coax  
.2 TNSMITTER FUNCTIONS  
d) the Jabber Timer - disables the Transmitter in case
longer than legal length packets  
The Tnsmitter has a differential input and an open collec-  
tor tput current driver. The differential input common  
de voltage is established by the CTI and should not be  
altered by external circuitry. The transformer coupling of  
g
TX will satisfy this condition. The driver meets all IEEE  
802.3/Ethernet Specifications for signal levels. Controlled  
3.1 RECEIVER FUNCTIONS  
The Receiver includes an input buffer, ab
4-pole Bessel low pass filter, a squelch cir
ential line driver.  
The buffer provides high and lo
pacitance to minimize s on thoax.  
g
rise and fall times (25 ns V 5 ns) minimize the higher  
harmonic components. The rise and fall times are matched  
to minimize jitter. The drive current levels of the DP8392C  
meet the tighter recommended limits of IEEE 802.3 and are  
set by a built-in bandgap reference and an external 1% re-  
sistor. An on chip isolation diode is provided to reduce the  
Transmitter’s coax load capacitance. For Ethernet compati-  
ble applications, an external isolation diode (see Figure 4 )  
may be added to further reduce coax load capacitance. In  
Cheapernet compatible applications the external diode is  
not required as the coax capacitive loading specifications  
are relaxed.  
The equalizer is a himpensates for  
the low pass effect of e result of the  
maximum length cabla flatband re-  
sponse at the signal frejitter.  
The 4-pole Bessel low pathe average DC  
level on the coax, which is uby both the Receiver  
squelch and the collision detection circuits.  
The Receiver squelch circuit prevents noise on the coax  
from falsely triggering the Receiver in the absence of the  
signal. At the beginning of the packet, the Receiver turns on  
when the DC level from the low pass filter is lower than the  
DC squelch threshold. However, at the end of the packet, a  
quick Receiver turn off is needed to reject dribble bits. This  
is accomplished by an AC timing circuit that reacts to high  
level signals of greater than typically 200 ns in duration. The  
The Transmitter squelch circuit rejects signals with pulse  
widths less than typically 20 ns (negative going), or with  
b
levels less than 175 mV. The Transmitter turns off at the  
end of the packet if the signal stays higher than 175 mV  
b
for more than approximately 300 ns. Figure 3 illustrates the  
Transmitter timing.  
2

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