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DP83932CVF-20 PDF预览

DP83932CVF-20

更新时间: 2024-02-14 12:26:09
品牌 Logo 应用领域
德州仪器 - TI 时钟局域网数据传输外围集成电路
页数 文件大小 规格书
98页 958K
描述
2 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, PQFP132, PLASTIC, QFP-132

DP83932CVF-20 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:BQFP, SPQFP132,1.1SQReach Compliance Code:unknown
风险等级:5.84JESD-30 代码:S-PQFP-G132
湿度敏感等级:3端子数量:132
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BQFP
封装等效代码:SPQFP132,1.1SQ封装形状:SQUARE
封装形式:FLATPACK电源:5 V
认证状态:Not Qualified子类别:Serial IO/Communication Controllers
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUADuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

DP83932CVF-20 数据手册

 浏览型号DP83932CVF-20的Datasheet PDF文件第2页浏览型号DP83932CVF-20的Datasheet PDF文件第3页浏览型号DP83932CVF-20的Datasheet PDF文件第4页浏览型号DP83932CVF-20的Datasheet PDF文件第5页浏览型号DP83932CVF-20的Datasheet PDF文件第6页浏览型号DP83932CVF-20的Datasheet PDF文件第7页 
July 1995  
DP83932C-20/25/33 MHz SONICTM  
Systems-Oriented Network Interface Controller  
General Description  
The SONIC (Systems-Oriented Network Interface Control-  
ler) is a second-generation Ethernet Controller designed to  
meet the demands of today’s high-speed 32- and 16-bit sys-  
tems. Its system interface operates with a high speed DMA  
that typically consumes less than 3% of the bus bandwidth  
(25 MHz bus clock). Selectable bus modes provide both big  
and little endian byte ordering and a clean interface to stan-  
dard microprocessors. The linked-list buffer management  
system of SONIC offers maximum flexibility in a variety of  
environments from PC-oriented adapters to high-speed  
motherboard designs. Furthermore, the SONIC integrates a  
fully-compatible IEEE 802.3 Encoder/Decoder (ENDEC) al-  
lowing for a simple 2-chip solution for Ethernet when the  
SONIC is paired with the DP8392 Coaxial Transceiver Inter-  
face or a 10BASE-T transceiver.  
management uses two areas in memory: one for indicating  
status and control information and the other for fetching  
packet data. The system can create a transmit queue allow-  
ing multiple packets to be transmitted from a single transmit  
command. The packet data can reside on any arbitrary byte  
boundary and can exist in several non-contiguous locations.  
Features  
Y
32-bit non-multiplexed address and data bus  
Y
High-speed, interruptible DMA  
Y
Linked-list buffer management maximizes flexibility  
Y
Two independent 32-byte transmit and receive FIFOs  
Y
Bus compatibility for all standard microprocessors  
Y
Supports big and little endian formats  
Y
Integrated IEEE 802.3 ENDEC  
For increased performance, the SONIC implements  
a
Y
Complete address filtering for up to 16 physical and/or  
multicast addresses  
unique buffer management scheme to efficiently process,  
receive and transmit packets in system memory. No inter-  
mediate packet copy is necessary. The receive buffer man-  
agement uses three areas in memory for (1) allocating addi-  
tional resources, (2) indicating status information, and (3)  
buffering packet data. During reception, the SONIC stores  
packets in the buffer area, then indicates receive status and  
control information in the descriptor area. The system allo-  
cates more memory resources to the SONIC by adding de-  
scriptors to the memory resource area. The transmit buffer  
Y
32-bit general-purpose timer  
Y
Full-duplex loopback diagnostics  
Y
Fabricated in low-power CMOS  
Y
132 PQFP package  
Y
Full network management facilities support the 802.3  
layer management standard  
Y
Integrated support for bridge and repeater applications  
System Diagram  
TL/F/10492–2  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
SONICTM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/10492  
RRD-B30M105/Printed in U. S. A.  

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