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DP83932BVF-MPC PDF预览

DP83932BVF-MPC

更新时间： 2024-02-18 13:40:53
品牌 Logo 应用领域
美国国家半导体 - NSC 网络接口控制器
页数 文件大小 规格书
96页 1046K
描述
IC 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, Serial IO/Communication Controller

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中文翻译

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DP83932BVF-MPC 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：QFP,针数：132
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.84地址总线宽度：32
边界扫描：NO总线兼容性：68030; 68020
最大时钟频率：20 MHz通信协议：ASYNC, BIT; SYNC, BYTE
数据编码/解码方法：NRZ; BIPH-LEVEL(MANCHESTER)最大数据传输速率：1.25 MBps
外部数据总线宽度：32JESD-30 代码：S-PQFP-G132
长度：24.13 mm低功率模式：YES
串行 I/O 数：1端子数量：132
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装形状：SQUARE封装形式：FLATPACK
座面最大高度：4.446 mm最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
宽度：24.13 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LAN

DP83932BVF-MPC 数据手册

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PRELIMINARY  
November 1995  
DP83916 SONICTM-16  
Systems-Oriented Network Interface Controller  
General Description  
The SONICTM-16 (Systems-Oriented Network Interface  
Controller) is a second-generation Ethernet Controller de-  
signed to meet the demands of today’s high-speed 16-bit  
systems. Its system interface operates with a high speed  
DMA that typically consumes less than 8% of the bus band-  
width. Selectable bus modes provide both big and little endi-  
an byte ordering and a clean interface to standard micro-  
processors. The linked-list buffer management system of  
SONIC-16 offers maximum flexibility in a variety of environ-  
ments from PC-oriented adapters to high-speed mother-  
board designs. Furthermore, the SONIC-16 integrates a ful-  
ly-compatible IEEE 802.3 Encoder/Decoder (ENDEC) al-  
lowing for a simple 2-chip solution for Ethernet when the  
SONIC-16 is paired with the DP8392 Coaxial Transceiver  
Interface.  
one for indicating status and control information and the  
other for fetching packet data. The system can create a  
transmit queue allowing multiple packets to be transmitted  
from a single transmit command. The packet data can re-  
side on any arbitrary byte boundary and can exist in several  
non-contiguous locations.  
Features  
Y
23-bit non-multiplexed address/16-bit data bus  
Y
High-speed, interruptible DMA  
Y
Linked-list buffer management maximizes flexibility  
Y
Two independent 32-byte transmit and receive FIFOs  
Y
Bus compatibility for all standard microprocessors  
Y
Supports big and little endian formats  
Y
Integrated IEEE 802.3 ENDEC  
For increased performance, the SONIC-16 implements a  
unique buffer management scheme to efficiently process  
receive and transmit packets in system memory. No inter-  
mediate packet copy is necessary. The receive buffer man-  
agement uses three areas in memory for (1) allocating addi-  
tional resources, (2) indicating status information, and (3)  
buffering packet data. During reception, the SONIC-16  
stores packets in the buffer area, then indicates receive  
status and control information in the descriptor area. The  
system allocates more memory resources to the SONIC-16  
by adding descriptors to the memory resource area. The  
transmit buffer management uses two areas in memory:  
Y
Complete address filtering for up to 16 physical and/or  
multicast addresses  
Y
32-bit general-purpose timer  
Y
Full-duplex loopback diagnostics  
Y
Fabricated in low-power CMOS  
Y
132 PQFP package  
Y
Full network management facilities support the IEEE  
802.3 layer management standard  
Y
Integrated support for bridge and repeater applications  
System Diagram  
IEEE 802.3 Ethernet/Thin-Ethernet/10BASE-T Station  
TL/F/11722–1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
RICTM and SONICTM-16 are trademarks of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/11722  
RRD-B30M16/Printed in U. S. A.  
1234567...96

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